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Henrik RydgårdandClaude Opus 5.5
e52cc38866
Sysreg (0xBC100000) gets the ME's reset bit (0x4C bit 2), the soft interrupt (0x44, which interrupts the other CPU: the ME's controller from the main CPU, PSP_MECODEC_INTR from the ME), the hardware mutex (0x48, each CPU sets its own bit only while the other's is clear) and the clock and config registers it writes. The ME's interrupt controller (0xBC300000, write-1-to-clear, mask at 8) answers the ME only. All of it is the ME's state and stays unhandled without an ME. On the ME: interrupts to EBase with EPC and EXL, halt sleeping until an unmasked interrupt, and Count, which doesn't run: it stays 0 across 10ms with ERL set after reset and with Status cleared, and reads back what was written. Reset keeps the GPRs and sets Status ERL/BEV/SR, which homebrew relies on: mcidclan's samples run C on the stack Sony's ME code left. The values are from a kernel probe on a PSP-1000 (sp 0x801FFFE0, COP0 22 = 1, Status 0x20500404, mfic 0, which doesn't gate interrupts). The main CPU runs base interrupt handlers the way interruptman calls them (a0 intno, a1 arg, a2 interrupted pc; -2 disables), and interrupt 31 has a stand-in for me_wrapper's handler, which homebrew releases first. While the ME is emulated, any main CPU code may access hardware registers: homebrew calls its own code in kernel mode through a kcall module. This is a stopgap (g_kernelModeAnywhere, marked HACK): kernel mode should be part of the CPU's state, switched on while a kernel module's export runs. The memcpy/memmove replacements copy through MMIO when an end is a register address, for code copied to the boot page. mcidclan's me-soft-interrupt sample now runs, counting each interrupt in both directions. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>