mirror of
https://github.com/hrydgard/ppsspp.git
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Henrik RydgårdandClaude Opus 5.5
ed25f9c436
MIST (and psp-media-engine-safe-task, and NJEMU through it) restart the ME through me_wrapper's bootstrap at 0xBFC00040, after patching it to point a0 at main RAM, which makes the firmware take its resume-from- sleep path: restore eDRAM from a0 and go back to the main loop. They then put a task's address in the firmware's command table with DMACplus and send a command with the soft interrupt. - The boot now leaves a bootstrap with 6.61's layout at 0xBFC00040, and a stand-in for me_wrapper's ME stub (which isn't loaded under HLE) that runs the image. - The firmware never sets Status.IE: it gates interrupts with mtic alone, so either one enables them now. Its main loop enables them for only a few instructions, so mtic takes a pending one right away. - Opcode 0x2C, which the resume path runs, is a no-op on the ME. - Sysreg 0x00 reads 0 (the bootstrap's debug handler check), 0x70 is kept, and the DDR flush register (0xBD000004) is always done. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
60 lines
2.4 KiB
C++
60 lines
2.4 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include "Common/CommonTypes.h"
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#include "Core/MIPS/MIPS.h"
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int MIPS_InterpretSingleStep(MIPSState *mips);
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namespace MIPSInt
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{
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void Int_Syscall(MIPSState *mips, MIPSOpcode op);
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void Int_mxc1(MIPSState *mips, MIPSOpcode op);
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void Int_Cop0(MIPSState *mips, MIPSOpcode op);
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void Int_Eret(MIPSState *mips, MIPSOpcode op);
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void Int_RelBranch(MIPSState *mips, MIPSOpcode op);
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void Int_RelBranchRI(MIPSState *mips, MIPSOpcode op);
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void Int_IType(MIPSState *mips, MIPSOpcode op);
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void Int_ITypeMem(MIPSState *mips, MIPSOpcode op);
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void Int_RType2(MIPSState *mips, MIPSOpcode op);
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void Int_RType3(MIPSState *mips, MIPSOpcode op);
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void Int_ShiftType(MIPSState *mips, MIPSOpcode op);
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void Int_MulDivType(MIPSState *mips, MIPSOpcode op);
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void Int_JumpType(MIPSState *mips, MIPSOpcode op);
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void Int_JumpRegType(MIPSState *mips, MIPSOpcode op);
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void Int_Allegrex2(MIPSState *mips, MIPSOpcode op);
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void Int_FPULS(MIPSState *mips, MIPSOpcode op);
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void Int_FPU3op(MIPSState *mips, MIPSOpcode op);
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void Int_FPU2op(MIPSState *mips, MIPSOpcode op);
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void Int_Allegrex(MIPSState *mips, MIPSOpcode op);
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void Int_FPUComp(MIPSState *mips, MIPSOpcode op);
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void Int_FPUBranch(MIPSState *mips, MIPSOpcode op);
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void Int_CallReplacement(MIPSState *mips, MIPSOpcode op);
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void Int_Special2(MIPSState *mips, MIPSOpcode op);
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void Int_Halt(MIPSState *mips, MIPSOpcode op);
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void Int_Me2C(MIPSState *mips, MIPSOpcode op);
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void Int_Special3(MIPSState *mips, MIPSOpcode op);
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void Int_Interrupt(MIPSState *mips, MIPSOpcode op);
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void Int_Cache(MIPSState *mips, MIPSOpcode op);
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void Int_Sync(MIPSState *mips, MIPSOpcode op);
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void Int_Break(MIPSState *mips, MIPSOpcode op);
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void Int_StoreSync(MIPSState *mips, MIPSOpcode op);
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}
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