ppsspp/Core/MIPS/IR/IRInst.h

#pragma once

#include <cstdint>
#include <vector>
#include <utility>

#include "Common/CommonTypes.h"
#include "Core/MIPS/MIPS.h"

// Basic IR
//
// This IR refers implicitly to the MIPS register set and is simple to interpret.
// To do real compiler things with it and do full-function compilation, it probably
// needs to be lifted to a higher IR first, before being lowered onto each target.
// But this gets rid of a lot of MIPS idiosyncrasies that makes it tricky, like
// delay slots, and is very suitable for translation into other IRs. Can of course
// even be directly JIT-ed, but the gains will probably be tiny over our older direct
// MIPS->target JITs.

// Ops beginning with "OI" are specialized for IR Interpreter use. These will not be produced
// for the IR JITs.

enum class IROp : uint8_t {
	SetConst,
	SetConstF,

	Mov,

	Add,
	Sub,
	Neg,
	Not,

	And,
	Or,
	Xor,

	AddConst,
	OptAddConst,
	SubConst,

	AndConst,
	OrConst,
	XorConst,
	OptAndConst,
	OptOrConst,

	Shl,
	Shr,
	Sar,
	Ror,

	// The shift is stored directly, not in the const table, so Imm instead of Const
	ShlImm,
	ShrImm,
	SarImm,
	RorImm,

	Slt,
	SltConst,
	SltU,
	SltUConst,

	Clz,

	// Conditional moves
	MovZ,
	MovNZ,

	Max,
	Min,

	// Byte swaps. All CPUs have native ones so worth keeping.
	BSwap16,  // Swaps both the high and low byte pairs.
	BSwap32,

	// Weird Hi/Lo semantics preserved. Too annoying to do something more generic.
	MtLo,
	MtHi,
	MfLo,
	MfHi,
	Mult,
	MultU,
	Madd,
	MaddU,
	Msub,
	MsubU,
	Div,
	DivU,

	// These take a constant from the pool as an offset.
	// Loads from a constant address can be represented by using r0.
	Load8,
	Load8Ext,
	Load16,
	Load16Ext,
	Load32,
	Load32Left,
	Load32Right,
	Load32Linked,
	LoadFloat,
	LoadVec4,

	Store8,
	Store16,
	Store32,
	Store32Left,
	Store32Right,
	Store32Conditional,
	StoreFloat,
	StoreVec4,

	// Kernel code's loads and stores, which may reach hardware registers (MMIO). See
	// ResolveKernelMemory.
	LoadKernel8,
	LoadKernel8Ext,
	LoadKernel16,
	LoadKernel16Ext,
	LoadKernel32,
	StoreKernel8,
	StoreKernel16,
	StoreKernel32,

	Ext8to32,
	Ext16to32,
	ReverseBits,

	FAdd,
	FSub,
	FMul,
	FDiv,
	FMin,
	FMax,

	FMov,
	FSqrt,
	FNeg,
	FAbs,
	FSign,

	FRound,
	FTrunc,
	FCeil,
	FFloor,

	FCvtWS,
	FCvtSW,
	FCvtScaledWS,
	FCvtScaledSW,

	FMovFromGPR,
	OptFCvtSWFromGPR,
	FMovToGPR,
	OptFMovToGPRShr8,
	// A conditional exit merged with the ExitToConst after it, which stays behind as the target
	// to take otherwise (in its constant).
	OptExitToConstIfEqElse,
	OptExitToConstIfNeqElse,
	OptExitToConstIfGtZElse,
	OptExitToConstIfGeZElse,
	OptExitToConstIfLtZElse,
	OptExitToConstIfLeZElse,

	FSat0_1,
	FSatMinus1_1,

	FpCondFromReg,
	FpCondToReg,
	FpCtrlFromReg,
	FpCtrlToReg,
	VfpuCtrlToReg,

	FCmp,

	FCmovVfpuCC,
	FCmpVfpuBit,
	FCmpVfpuAggregate,

	// Rounding Mode
	RestoreRoundingMode,
	ApplyRoundingMode,
	UpdateRoundingMode,

	SetCtrlVFPU,
	SetCtrlVFPUReg,
	SetCtrlVFPUFReg,

	// 4-wide instructions to assist SIMD.
	// Can of course add a pass to break them up if a target does not
	// support SIMD.
	Vec4Init,
	Vec4Shuffle,
	Vec4Blend,
	Vec4Mov,
	Vec4Add,
	Vec4Sub,
	Vec4Mul,
	Vec4Div,
	Vec4Scale,
	Vec4VfpuDot,  // The VFPU's own dot product, bit-exact (vfpu_dot).
	Vec4VfpuMultiDot,  // Four of them against one vector, see IRMultiDot.
	Vec4Neg,
	Vec4Abs,
	// vmin/vmax (by vfpu_minmax_key, a tie taking src2), vslt and vsge (1.0 or 0.0, 0.0 for NaN).
	Vec4Min,
	Vec4Max,
	Vec4Slt,
	Vec4Sge,
	// vi2f: each lane's int to float, divided by 2^src2.
	Vec4CvtScaledSW,

	// vx2i
	Vec2Unpack16To31,  // Note that the result is shifted down by 1, hence 31
	Vec2Unpack16To32,
	Vec4Unpack8To32,
	Vec4DuplicateUpperBitsAndShift1,  // Bizarro vuc2i behaviour, in an instruction. Split?
	// vi2x. The 31 ones take bits 30 and down, after clamping negative lanes to zero (vi2uc, vi2us).
	Vec4Pack31To8,
	Vec4Pack32To8,
	Vec2Pack31To16,
	Vec2Pack32To16,

	// Slow special functions. Used on singles.
	FSin,
	FCos,
	FRSqrt,  // vrsq, bit-exact with the PSP
	FRecip,  // vrcp, bit-exact with the PSP
	FAsin,
	FVSqrt,  // vsqrt, bit-exact with the PSP (FSqrt is the FPU's IEEE sqrt.s)
	FExp2,  // vexp2, bit-exact with the PSP
	FLog2,  // vlog2, bit-exact with the PSP
	FHalfToFloat,  // vh2f of the lower (src2 = 0) or upper (src2 = 1) half of src1
	FSinCos,  // dest = sin(src1), dest + 1 = cos(src1), from one argument reduction

	// Fake/System instructions
	Interpret,

	// Emit this before you exit. Semantic is to set the downcount
	// that will be used at the actual exit.
	Downcount,  // src1 + (src2<<8)

	// End-of-basic-block.
	ExitToConst,   // 0, const, downcount
	ExitToReg,
	ExitToConstIfEq,  // const, reg1, reg2
	ExitToConstIfNeq, // const, reg1, reg2
	ExitToConstIfGtZ,  // const, reg1, 0
	ExitToConstIfGeZ,  // const, reg1, 0
	ExitToConstIfLtZ,  // const, reg1, 0
	ExitToConstIfLeZ,  // const, reg1, 0

	ExitToConstIfFpTrue,
	ExitToConstIfFpFalse,
	ExitToPC,  // Used after a syscall to give us a way to do things before returning.

	Syscall,  // Needs the syscall instruction work in the constant.
	SyscallUnresolved,  // Used when the syscall is not resolved at compile time. PC in the constant.
	SetPC,  // hack to make syscall returns work
	SetPCConst,  // hack to make replacement know PC
	CallReplacement,
	Break,

	// Debugging breakpoints.
	Breakpoint,
	MemoryCheck,

	ValidateAddress8,
	ValidateAddress16,
	ValidateAddress32,
	ValidateAddress128,

	// Tracing support.
	LogIRBlock,

	Nop,
	Bad,
};

enum IRComparison {
	Greater,
	GreaterEqual,
	Less,
	LessEqual,
	Equal,
	NotEqual,
	Bad,
};

// Some common vec4 constants.
enum class Vec4Init {
	AllZERO,
	AllONE,
	AllMinusONE,
	Set_1000,
	Set_0100,
	Set_0010,
	Set_0001,
};

// The source lane of dest lane i in a Vec4Shuffle, two bits per lane like a VFPU prefix's swizzle.
inline int Vec4ShuffleLane(u32 shuffle, int i) {
	return (shuffle >> (i * 2)) & 3;
}

enum class IRRoundMode : uint8_t {
	RINT_0 = 0,
	CAST_1 = 1,
	CEIL_2 = 2,
	FLOOR_3 = 3,
};

// Hm, unused
inline IRComparison Invert(IRComparison comp) {
	switch (comp) {
	case IRComparison::Equal: return IRComparison::NotEqual;
	case IRComparison::NotEqual: return IRComparison::Equal;
	case IRComparison::Greater: return IRComparison::LessEqual;
	case IRComparison::GreaterEqual: return IRComparison::Less;
	case IRComparison::Less: return IRComparison::GreaterEqual;
	case IRComparison::LessEqual: return IRComparison::Greater;
	default:
		return IRComparison::Bad;
	}
}

inline IROp ComparisonToExit(IRComparison comp) {
	switch (comp) {
	case IRComparison::Equal: return IROp::ExitToConstIfEq;
	case IRComparison::NotEqual: return IROp::ExitToConstIfNeq;
	case IRComparison::Greater: return IROp::ExitToConstIfGtZ;
	case IRComparison::GreaterEqual: return IROp::ExitToConstIfGeZ;
	case IRComparison::Less: return IROp::ExitToConstIfLtZ;
	case IRComparison::LessEqual: return IROp::ExitToConstIfLeZ;
	default:
		return IROp::Break;
	}
}

enum IRFpCompareMode {
	False = 0,
	EitherUnordered,
	EqualOrdered, // eq,  seq (equal, ordered)
	EqualUnordered, // ueq, ngl (equal, unordered)
	LessOrdered, // olt, lt (less than, ordered)
	LessUnordered, // ult, nge (less than, unordered)
	LessEqualOrdered, // ole, le (less equal, ordered)
	LessEqualUnordered, // ule, ngt (less equal, unordered)
};

typedef u8 IRReg;

// Vec4VfpuMultiDot dest, block, v, constant: lane k of dest is vfpu_dot() of lane k of the 4x4 block
// of regs (16 in a row) and v, over the first IRMULTIDOT_TERMS(constant) terms (the rest are zero in
// both). Lane k is the block's row k (block[4 * i + k]), or with IRMULTIDOT_TRANSPOSED, its Vec4 k
// (block[4 * k + i]).
enum : u32 {
	IRMULTIDOT_TERMS_MASK = 0x7,
	IRMULTIDOT_TRANSPOSED = 0x10,
};
inline int IRMULTIDOT_TERMS(u32 constant) { return (int)(constant & IRMULTIDOT_TERMS_MASK); }

enum : IRReg {
	IRTEMP_0 = 192,
	IRTEMP_1,
	IRTEMP_2,
	IRTEMP_3,
	IRTEMP_LHS,  // Reserved for use in branches
	IRTEMP_RHS,  // Reserved for use in branches
	IRTEMP_LR_ADDR,  // Reserved for left/right loads and stores.
	IRTEMP_LR_VALUE, // Reserved for left/right loads and stores.
	IRTEMP_LR_MASK,  // Reserved for left/right loads and stores.
	IRTEMP_LR_SHIFT, // Reserved for left/right loads and stores.

	IRVTEMP_PFX_S = 224 - 32,  // Relative to the FP regs
	IRVTEMP_PFX_T = 228 - 32,
	IRVTEMP_PFX_D = 232 - 32,
	IRVTEMP_0 = 236 - 32,

	// Hacky way to get to other state
	IRREG_VFPU_CTRL_BASE = 208,
	IRREG_VFPU_CC = 211,
	IRREG_LO = 242,  // offset of lo in MIPSState / 4
	IRREG_HI = 243,
	IRREG_FCR31 = 244,
	IRREG_FPCOND = 245,
	IRREG_LLBIT = 250,
};

enum IRFlags {
	// Uses src3, not dest.
	IRFLAG_SRC3 = 0x0001,
	// Uses src3 AND dest (i.e. mutates dest.)
	IRFLAG_SRC3DST = 0x0002,
	// Exit instruction (maybe conditional.)
	IRFLAG_EXIT = 0x0004,
	// Instruction like Interpret which may read anything, but not an exit.
	IRFLAG_BARRIER = 0x0008,
};

struct IRMeta {
	IROp op;
	const char *name;
	char types[5];  // GGG
	u32 flags;
};

// 64 bits.
struct IRInst {
	IROp op;
	union {
		IRReg dest;
		IRReg src3;
	};
	IRReg src1;
	IRReg src2;
	u32 constant;
};

// Returns the new PC. With the block arena, exits go straight on to the next compiled block while
// downcount lasts, instead of returning.
u32 IRInterpret(MIPSState *ms, const IRInst *inst, const IRInst *chainArena = nullptr);

// Each IR block gets a constant pool.
class IRWriter {
public:
	IRWriter &operator =(const IRWriter &w) {
		insts_ = w.insts_;
		return *this;
	}
	IRWriter &operator =(IRWriter &&w) noexcept {
		insts_ = std::move(w.insts_);
		return *this;
	}

	void Write(IROp op, u8 dst = 0, u8 src1 = 0, u8 src2 = 0, u32 constant = 0);
	void WriteFC(IROp op, u8 dst, u8 src1, u8 src2, float fconstant);

	void WriteSetConstant(u8 dst, u32 value);
	void WriteSetConstantFloat(u8 dst, float value);
	void Write(IRInst inst) {
		insts_.push_back(inst);
	}

	void Reserve(size_t s) {
		insts_.reserve(s);
	}
	void Clear() {
		insts_.clear();
	}
	void ReplaceConstant(size_t instNumber, u32 newConstant);

	const std::vector<IRInst> &GetInstructions() const { return insts_; }

private:
	std::vector<IRInst> insts_;
};

// How far IRFrontend compiles on past conditional branches. The interpreter ends its blocks in the
// same places (see GetIRBlockEnd in MIPSTables.cpp), so events happen at the same instruction.
constexpr bool IR_CONTINUE_BRANCHES = true;
constexpr int IR_MAX_CONTINUED_INSTRUCTIONS = 96;
constexpr int IR_MAX_CONTINUED_BRANCHES = 8;

struct IROptions {
	uint32_t disableFlags;
	bool unalignedLoadStore;
	bool unalignedLoadStoreVec4;
	bool preferVec4;
	bool optimizeForInterpreter;
	// The backend has Vec4VfpuMultiDot.
	bool vfpuMultiDot;
	// Compile on past conditional branches (see IRFrontend::CanContinuePastBranch). Always
	// IR_CONTINUE_BRANCHES, which the interpreter follows.
	bool continueBranches;
	// The backend has Vec4Min, Vec4Max, Vec4Slt, Vec4Sge and Vec4CvtScaledSW.
	bool moreVec4Ops;
};

const IRMeta *GetIRMeta(IROp op);
void DisassembleIR(char *buf, size_t bufsize, IRInst inst);
void InitIR();