mirror of
https://github.com/hrydgard/ppsspp.git
synced 2026-10-03 09:45:25 +02:00
327 lines
8.7 KiB
C++
327 lines
8.7 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ArmRegCache.h"
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#include "ArmEmitter.h"
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#include "ArmJit.h"
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#if defined(MAEMO)
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#include "stddef.h"
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#endif
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using namespace ArmGen;
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ArmRegCache::ArmRegCache(MIPSState *mips, MIPSComp::ArmJitOptions *options) : mips_(mips), options_(options) {
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}
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void ArmRegCache::Init(ARMXEmitter *emitter) {
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emit_ = emitter;
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}
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void ArmRegCache::Start(MIPSAnalyst::AnalysisResults &stats) {
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for (int i = 0; i < NUM_ARMREG; i++) {
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ar[i].mipsReg = -1;
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ar[i].isDirty = false;
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}
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for (int i = 0; i < NUM_MIPSREG; i++) {
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mr[i].loc = ML_MEM;
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mr[i].reg = INVALID_REG;
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mr[i].imm = -1;
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mr[i].spillLock = false;
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}
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}
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const ARMReg *ArmRegCache::GetMIPSAllocationOrder(int &count) {
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// Note that R0 is reserved as scratch for now.
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// R1 could be used as it's only used for scratch outside "regalloc space" now.
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// R12 is also potentially usable.
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// R4-R7 are registers we could use for static allocation or downcount.
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// R8 is used to preserve flags in nasty branches.
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// R9 and upwards are reserved for jit basics.
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if (options_->downcountInRegister) {
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static const ARMReg allocationOrder[] = {
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R2, R3, R4, R5, R6, R12,
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};
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count = sizeof(allocationOrder) / sizeof(const int);
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return allocationOrder;
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} else {
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static const ARMReg allocationOrder2[] = {
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R2, R3, R4, R5, R6, R7, R12,
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};
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count = sizeof(allocationOrder2) / sizeof(const int);
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return allocationOrder2;
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}
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}
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void ArmRegCache::FlushBeforeCall() {
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// R4-R11 are preserved. Others need flushing.
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FlushArmReg(R2);
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FlushArmReg(R3);
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FlushArmReg(R12);
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}
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// TODO: Somewhat smarter spilling - currently simply spills the first available, should do
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// round robin or FIFO or something.
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ARMReg ArmRegCache::MapReg(MIPSReg mipsReg, int mapFlags) {
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// Let's see if it's already mapped. If so we just need to update the dirty flag.
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// We don't need to check for ML_NOINIT because we assume that anyone who maps
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// with that flag immediately writes a "known" value to the register.
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if (mr[mipsReg].loc == ML_ARMREG) {
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if (ar[mr[mipsReg].reg].mipsReg != mipsReg) {
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ERROR_LOG(JIT, "Register mapping out of sync! %i", mipsReg);
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}
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if (mapFlags & MAP_DIRTY) {
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ar[mr[mipsReg].reg].isDirty = true;
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}
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return (ARMReg)mr[mipsReg].reg;
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}
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// Okay, not mapped, so we need to allocate an ARM register.
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int allocCount;
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const ARMReg *allocOrder = GetMIPSAllocationOrder(allocCount);
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allocate:
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for (int i = 0; i < allocCount; i++) {
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int reg = allocOrder[i];
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if (ar[reg].mipsReg == -1) {
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// That means it's free. Grab it, and load the value into it (if requested).
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ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false;
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if (!(mapFlags & MAP_NOINIT)) {
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if (mipsReg == 0) {
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// If we get a request to load the zero register, at least we won't spend
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// time on a memory access...
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emit_->MOV((ARMReg)reg, 0);
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} else {
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if (mr[mipsReg].loc == ML_MEM) {
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emit_->LDR((ARMReg)reg, CTXREG, GetMipsRegOffset(mipsReg));
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} else if (mr[mipsReg].loc == ML_IMM) {
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emit_->MOVI2R((ARMReg)reg, mr[mipsReg].imm);
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ar[reg].isDirty = true; // IMM is always dirty.
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}
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}
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}
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ar[reg].mipsReg = mipsReg;
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mr[mipsReg].loc = ML_ARMREG;
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mr[mipsReg].reg = (ARMReg)reg;
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return (ARMReg)reg;
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}
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}
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// Still nothing. Let's spill a reg and goto 10.
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// TODO: Use age or something to choose which register to spill?
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// TODO: Spill dirty regs first? or opposite?
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int bestToSpill = -1;
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for (int i = 0; i < allocCount; i++) {
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int reg = allocOrder[i];
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if (ar[reg].mipsReg != -1 && mr[ar[reg].mipsReg].spillLock)
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continue;
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bestToSpill = reg;
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break;
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}
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if (bestToSpill != -1) {
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// ERROR_LOG(JIT, "Out of registers at PC %08x - spills register %i.", mips_->pc, bestToSpill);
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FlushArmReg((ARMReg)bestToSpill);
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goto allocate;
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}
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// Uh oh, we have all them spilllocked....
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ERROR_LOG(JIT, "Out of spillable registers at PC %08x!!!", mips_->pc);
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return INVALID_REG;
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}
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void ArmRegCache::MapInIn(MIPSReg rd, MIPSReg rs) {
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SpillLock(rd, rs);
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MapReg(rd);
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MapReg(rs);
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ReleaseSpillLocks();
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}
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void ArmRegCache::MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad) {
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SpillLock(rd, rs);
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bool load = !avoidLoad || rd == rs;
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MapReg(rd, MAP_DIRTY | (load ? 0 : MAP_NOINIT));
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MapReg(rs);
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ReleaseSpillLocks();
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}
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void ArmRegCache::MapDirtyInIn(MIPSReg rd, MIPSReg rs, MIPSReg rt, bool avoidLoad) {
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SpillLock(rd, rs, rt);
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bool load = !avoidLoad || (rd == rs || rd == rt);
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MapReg(rd, MAP_DIRTY | (load ? 0 : MAP_NOINIT));
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MapReg(rt);
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MapReg(rs);
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ReleaseSpillLocks();
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}
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void ArmRegCache::MapDirtyDirtyInIn(MIPSReg rd1, MIPSReg rd2, MIPSReg rs, MIPSReg rt, bool avoidLoad) {
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SpillLock(rd1, rd2, rs, rt);
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bool load1 = !avoidLoad || (rd1 == rs || rd1 == rt);
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bool load2 = !avoidLoad || (rd2 == rs || rd2 == rt);
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MapReg(rd1, MAP_DIRTY | (load1 ? 0 : MAP_NOINIT));
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MapReg(rd2, MAP_DIRTY | (load2 ? 0 : MAP_NOINIT));
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MapReg(rt);
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MapReg(rs);
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ReleaseSpillLocks();
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}
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void ArmRegCache::FlushArmReg(ARMReg r) {
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if (ar[r].mipsReg == -1) {
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// Nothing to do, reg not mapped.
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return;
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}
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if (ar[r].mipsReg != -1) {
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if (ar[r].isDirty && mr[ar[r].mipsReg].loc == ML_ARMREG)
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emit_->STR(r, CTXREG, GetMipsRegOffset(ar[r].mipsReg));
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// IMMs won't be in an ARM reg.
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mr[ar[r].mipsReg].loc = ML_MEM;
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mr[ar[r].mipsReg].reg = INVALID_REG;
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mr[ar[r].mipsReg].imm = 0;
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} else {
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ERROR_LOG(JIT, "Dirty but no mipsreg?");
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}
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ar[r].isDirty = false;
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ar[r].mipsReg = -1;
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}
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void ArmRegCache::DiscardR(MIPSReg r) {
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if (mr[r].loc == ML_ARMREG) {
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ARMReg a = mr[r].reg;
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ar[a].isDirty = false;
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ar[a].mipsReg = -1;
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mr[r].reg = INVALID_REG;
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mr[r].loc = ML_MEM;
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mr[r].imm = 0;
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}
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}
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void ArmRegCache::FlushR(MIPSReg r) {
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switch (mr[r].loc) {
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case ML_IMM:
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// IMM is always "dirty".
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if (r != 0) {
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emit_->MOVI2R(R0, mr[r].imm);
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emit_->STR(R0, CTXREG, GetMipsRegOffset(r));
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}
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break;
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case ML_ARMREG:
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if (mr[r].reg == INVALID_REG) {
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ERROR_LOG(JIT, "FlushMipsReg: MipsReg had bad ArmReg");
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}
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if (ar[mr[r].reg].isDirty) {
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if (r != 0) {
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emit_->STR((ARMReg)mr[r].reg, CTXREG, GetMipsRegOffset(r));
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}
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ar[mr[r].reg].isDirty = false;
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}
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ar[mr[r].reg].mipsReg = -1;
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break;
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case ML_MEM:
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// Already there, nothing to do.
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break;
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default:
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//BAD
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break;
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}
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mr[r].loc = ML_MEM;
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mr[r].reg = INVALID_REG;
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mr[r].imm = 0;
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}
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void ArmRegCache::FlushAll() {
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for (int i = 0; i < NUM_MIPSREG; i++) {
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FlushR(i);
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}
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// Sanity check
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for (int i = 0; i < NUM_ARMREG; i++) {
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if (ar[i].mipsReg != -1) {
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ERROR_LOG(JIT, "Flush fail: ar[%i].mipsReg=%i", i, ar[i].mipsReg);
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}
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}
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}
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void ArmRegCache::SetImm(MIPSReg r, u32 immVal) {
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if (r == 0)
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ERROR_LOG(JIT, "Trying to set immediate %08x to r0", immVal);
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// Zap existing value if cached in a reg
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if (mr[r].loc == ML_ARMREG) {
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ar[mr[r].reg].mipsReg = -1;
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ar[mr[r].reg].isDirty = false;
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}
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mr[r].loc = ML_IMM;
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mr[r].imm = immVal;
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mr[r].reg = INVALID_REG;
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}
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bool ArmRegCache::IsImm(MIPSReg r) const {
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if (r == 0) return true;
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return mr[r].loc == ML_IMM;
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}
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u32 ArmRegCache::GetImm(MIPSReg r) const {
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if (r == 0) return 0;
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if (mr[r].loc != ML_IMM) {
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ERROR_LOG(JIT, "Trying to get imm from non-imm register %i", r);
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}
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return mr[r].imm;
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}
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int ArmRegCache::GetMipsRegOffset(MIPSReg r) {
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if (r < 32)
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return r * 4;
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switch (r) {
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case MIPSREG_HI:
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return offsetof(MIPSState, hi);
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case MIPSREG_LO:
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return offsetof(MIPSState, lo);
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}
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ERROR_LOG(JIT, "bad mips register %i", r);
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return 0; // or what?
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}
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void ArmRegCache::SpillLock(MIPSReg r1, MIPSReg r2, MIPSReg r3, MIPSReg r4) {
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mr[r1].spillLock = true;
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if (r2 != -1) mr[r2].spillLock = true;
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if (r3 != -1) mr[r3].spillLock = true;
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if (r4 != -1) mr[r4].spillLock = true;
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}
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void ArmRegCache::ReleaseSpillLocks() {
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for (int i = 0; i < NUM_MIPSREG; i++) {
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mr[i].spillLock = false;
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}
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}
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void ArmRegCache::ReleaseSpillLock(MIPSReg reg) {
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mr[reg].spillLock = false;
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}
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ARMReg ArmRegCache::R(int mipsReg) {
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if (mr[mipsReg].loc == ML_ARMREG) {
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return (ARMReg)mr[mipsReg].reg;
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} else {
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ERROR_LOG(JIT, "Reg %i not in arm reg. compilerPC = %08x", mipsReg, compilerPC_);
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return INVALID_REG; // BAAAD
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}
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}
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