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https://github.com/hrydgard/ppsspp.git
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Henrik RydgårdandClaude Opus 5.5
4849ef020e
srl/srlv rotate when the low bit of their unused field (rs or sa) is set and shift when it's clear, whatever the other bits hold (cpu/cpu_alu/shift_encodings). The interpreter treated values above 1 as invalid and the other cores shifted. The Allegrex bit ops decode only some bits of sa, so all 32 values are one of wsbh, wsbw, seb, seh and bitrev (cpu/cpu_alu/allegrex_encodings). AllegrexBitOp() gives the canonical one for every core. Special3 function 0x18 does nothing on the PSP, where it was decoded as an alias of 0x20. The interpreter dispatch is regenerated, and its generator now lists each instruction name once. CPUEquivalence no longer skips the srl/srlv encodings. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
102 lines
3.6 KiB
C++
102 lines
3.6 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include "Common/CommonTypes.h"
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#include "Common/Data/Convert/SmallDataConvert.h"
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#include "Core/MIPS/MIPS.h"
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// Invalid branch target address
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#define INVALIDTARGET 0xFFFFFFFF
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#define MIPS_MAKE_B(offs) (0x10000000 | ((offs) & 0xFFFF))
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#define MIPS_MAKE_J(addr) (0x08000000 | ((addr)>>2))
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#define MIPS_MAKE_JAL(addr) (0x0C000000 | ((addr)>>2))
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#define MIPS_MAKE_JR_RA() (0x03e00008)
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#define MIPS_MAKE_NOP() (0)
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#define MIPS_MAKE_BNEZ(pc, addr, rs) (0x14000000 | (rs << 21) | (u32)(((int)(addr - (pc + 4)) >> 2) & 0xFFFF))
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#define MIPS_MAKE_ADDIU(dreg, sreg, immval) ((9 << 26) | ((dreg) << 16) | ((sreg) << 21) | (immval))
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#define MIPS_MAKE_LUI(reg, immval) (0x3c000000 | ((reg) << 16) | (immval))
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#define MIPS_MAKE_ORI(rt, rs, immval) (0x34000000 | ((rs) << 21) | ((rt) << 16) | (immval))
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#define MIPS_MAKE_LW(rt, rs, immval) (0x8c000000 | ((rs) << 21) | ((rt) << 16) | (immval))
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#define MIPS_MAKE_SYSCALL(module, function) GetSyscallOp(module, GetNibByName(module, function))
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#define MIPS_MAKE_BREAK(n) (((n) << 6) | 13) // ! :)
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#define MIPS_GET_OP(op) ((op>>26) & 0x3F)
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#define MIPS_GET_FUNC(op) (op & 0x3F)
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#define MIPS_GET_SA(op) ((op>>6) & 0x1F)
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#define MIPS_GET_RS(op) MIPSGPReg((op>>21) & 0x1F)
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#define MIPS_GET_RT(op) MIPSGPReg((op>>16) & 0x1F)
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#define MIPS_GET_RD(op) MIPSGPReg((op>>11) & 0x1F)
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#define MIPS_GET_FS(op) ((op>>11) & 0x1F)
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#define MIPS_GET_FT(op) ((op>>16) & 0x1F)
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#define MIPS_GET_FD(op) ((op>>6 ) & 0x1F)
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#define MIPS_GET_VD(op) (op & 0x7F)
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#define MIPS_GET_VS(op) ((op>>8) & 0x7F)
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#define MIPS_GET_VT(op) ((op>>16) & 0x7F)
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// ctc1 to fcr31, the only instruction that changes the guest's rounding mode and flush-to-zero.
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#define MIPS_IS_CTC1_FCR31(op) (((op) & 0xFFE0F800) == 0x44C0F800)
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inline int32_t SignExtend8ToS32(MIPSOpcode op) {
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return SignExtend8ToS32(op.encoding);
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}
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inline uint32_t SignExtend8ToU32(MIPSOpcode op) {
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return SignExtend8ToU32(op.encoding);
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}
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inline int32_t SignExtend16ToS32(MIPSOpcode op) {
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return SignExtend16ToS32(op.encoding);
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}
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inline uint32_t SignExtend16ToU32(MIPSOpcode op) {
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return SignExtend16ToU32(op.encoding);
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}
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// The Allegrex bit ops (special3, function 0x20) only decode some bits of the sa field, so every
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// value is one of them (cpu/cpu_alu/allegrex_encodings). Returns the canonical sa: 2 wsbh, 3 wsbw,
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// 16 seb, 20 bitrev, 24 seh.
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inline int AllegrexBitOp(MIPSOpcode op) {
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int sa = (op >> 6) & 31;
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if (!(sa & 0x10)) {
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return 2 | (sa & 1);
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}
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if (sa & 4) {
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return 20;
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}
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return (sa & 8) ? 24 : 16;
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}
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namespace MIPSCodeUtils
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{
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u32 GetCallTarget(u32 addr);
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u32 GetBranchTarget(u32 addr);
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// Ignores bltzal/etc. instructions that change RA.
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u32 GetBranchTargetNoRA(u32 addr);
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u32 GetBranchTargetNoRA(u32 addr, MIPSOpcode op);
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u32 GetJumpTarget(u32 addr);
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u32 GetSureBranchTarget(u32 addr);
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bool IsVFPUBranch(MIPSOpcode op);
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bool IsBranch(MIPSOpcode op);
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}
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