mirror of
https://github.com/hrydgard/ppsspp.git
synced 2026-10-14 15:00:30 +02:00
Henrik RydgårdandClaude Opus 5.5
4849ef020e
srl/srlv rotate when the low bit of their unused field (rs or sa) is set and shift when it's clear, whatever the other bits hold (cpu/cpu_alu/shift_encodings). The interpreter treated values above 1 as invalid and the other cores shifted. The Allegrex bit ops decode only some bits of sa, so all 32 values are one of wsbh, wsbw, seb, seh and bitrev (cpu/cpu_alu/allegrex_encodings). AllegrexBitOp() gives the canonical one for every core. Special3 function 0x18 does nothing on the PSP, where it was decoded as an alias of 0x20. The interpreter dispatch is regenerated, and its generator now lists each instruction name once. CPUEquivalence no longer skips the srl/srlv encodings. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
770 lines
18 KiB
C++
770 lines
18 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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// AUTO-GENERATED by `PPSSPPHeadless --generate-interpreter-dispatch` from the
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// tables in MIPSTables.cpp - do not hand-edit, regenerate instead.
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/Interpreter.h"
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#include "Core/MIPS/InterpreterVFPU.h"
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// Returns the cycle count consumed, or -1 if op isn't a recognized instruction -
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// callers must fall back to MIPSInterpret() themselves in that case.
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int ExecInstruction(MIPSState *mips, MIPSOpcode op) {
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switch ((op.encoding >> 26) & 0x3f) {
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case 0:
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{
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switch ((op.encoding >> 0) & 0x3f) {
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// sll, srl, sra, sllv, srlv, srav
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case 0:
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case 2:
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case 3:
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case 4:
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case 6:
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case 7:
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MIPSInt::Int_ShiftType(mips, op);
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return 1;
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// jr, jalr
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case 8:
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case 9:
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MIPSInt::Int_JumpRegType(mips, op);
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return 1;
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// movz, movn, add, addu, sub, subu, and, or, xor, nor, slt, sltu, max, min
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case 10:
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case 11:
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case 32:
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case 33:
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case 34:
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case 35:
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case 36:
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case 37:
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case 38:
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case 39:
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case 42:
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case 43:
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case 44:
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case 45:
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MIPSInt::Int_RType3(mips, op);
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return 1;
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// syscall
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case 12:
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MIPSInt::Int_Syscall(mips, op);
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return 1;
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// break
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case 13:
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MIPSInt::Int_Break(mips, op);
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return 1;
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// sync
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case 15:
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MIPSInt::Int_Sync(mips, op);
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return 1;
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// mfhi, mthi, mflo, mtlo, mult, multu, div, divu, madd, maddu, msub, msubu
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case 16:
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case 17:
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case 18:
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case 19:
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case 24:
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case 25:
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case 26:
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case 27:
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case 28:
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case 29:
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case 46:
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case 47:
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MIPSInt::Int_MulDivType(mips, op);
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return 1;
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// clz, clo
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case 22:
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case 23:
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MIPSInt::Int_RType2(mips, op);
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return 1;
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default:
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return -1;
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}
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}
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case 1:
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{
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switch ((op.encoding >> 16) & 0x1f) {
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// bltz, bgez, bltzl, bgezl, bltzal, bgezal, bltzall, bgezall
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case 0:
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case 1:
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case 2:
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case 3:
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case 16:
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case 17:
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case 18:
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case 19:
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MIPSInt::Int_RelBranchRI(mips, op);
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return 1;
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default:
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return -1;
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}
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}
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// j, jal
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case 2:
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case 3:
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MIPSInt::Int_JumpType(mips, op);
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return 1;
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// beq, bne, blez, bgtz, beql, bnel, blezl, bgtzl
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case 4:
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case 5:
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case 6:
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case 7:
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case 20:
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case 21:
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case 22:
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case 23:
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MIPSInt::Int_RelBranch(mips, op);
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return 1;
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// addi, addiu, slti, sltiu, andi, ori, xori, lui
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case 8:
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case 9:
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case 10:
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case 11:
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case 12:
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case 13:
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case 14:
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case 15:
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MIPSInt::Int_IType(mips, op);
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return 1;
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case 16:
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{
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switch ((op.encoding >> 21) & 0x1f) {
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// mfc0, mtc0, rdpgpr, mfmc0, wrpgpr
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case 0:
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case 4:
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case 10:
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case 11:
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case 14:
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MIPSInt::Int_Cop0(mips, op);
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return 1;
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case 16:
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case 17:
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case 18:
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case 19:
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case 20:
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case 21:
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case 22:
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case 23:
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case 24:
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case 25:
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case 26:
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case 27:
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case 28:
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case 29:
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case 30:
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case 31:
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{
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return -1;
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}
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default:
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return -1;
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}
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}
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case 17:
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{
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switch ((op.encoding >> 21) & 0x1f) {
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// mfc1, cfc1, mtc1, ctc1
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case 0:
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case 2:
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case 4:
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case 6:
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MIPSInt::Int_mxc1(mips, op);
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return 1;
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case 8:
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{
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switch ((op.encoding >> 16) & 0x1f) {
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// bc1f, bc1t, bc1fl, bc1tl
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case 0:
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case 1:
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case 2:
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case 3:
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MIPSInt::Int_FPUBranch(mips, op);
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return 1;
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default:
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return -1;
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}
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}
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case 16:
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{
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switch ((op.encoding >> 0) & 0x3f) {
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// add.s, sub.s, mul.s
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case 0:
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case 1:
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case 2:
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MIPSInt::Int_FPU3op(mips, op);
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return 1;
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// div.s
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case 3:
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MIPSInt::Int_FPU3op(mips, op);
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return 29;
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// sqrt.s, abs.s, mov.s, neg.s, round.w.s, trunc.w.s, ceil.w.s, floor.w.s, cvt.w.s
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case 4:
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case 5:
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case 6:
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case 7:
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case 12:
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case 13:
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case 14:
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case 15:
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case 36:
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MIPSInt::Int_FPU2op(mips, op);
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return 1;
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// dis.int
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case 38:
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MIPSInt::Int_Interrupt(mips, op);
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return 1;
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// c.f.s, c.un.s, c.eq.s, c.ueq.s, c.olt.s, c.ult.s, c.ole.s, c.ule.s, c.sf.s, c.ngle.s, c.seq.s, c.ngl.s, c.lt.s, c.nge.s, c.le.s, c.ngt.s
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case 48:
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case 49:
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case 50:
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case 51:
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case 52:
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case 53:
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case 54:
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case 55:
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case 56:
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case 57:
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case 58:
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case 59:
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case 60:
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case 61:
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case 62:
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case 63:
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MIPSInt::Int_FPUComp(mips, op);
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return 1;
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default:
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return -1;
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}
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}
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case 20:
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{
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switch ((op.encoding >> 0) & 0x3f) {
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// cvt.s.w
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case 32:
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MIPSInt::Int_FPU2op(mips, op);
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return 1;
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default:
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return -1;
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}
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}
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default:
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return -1;
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}
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}
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case 18:
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{
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switch ((op.encoding >> 21) & 0x1f) {
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// mfv, mtv
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case 3:
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case 7:
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MIPSInt::Int_Mftv(mips, op);
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return 2;
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case 8:
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{
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switch ((op.encoding >> 16) & 0x3) {
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// bvf, bvt, bvfl, bvtl
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case 0:
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case 1:
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case 2:
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case 3:
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MIPSInt::Int_VBranch(mips, op);
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return 2;
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default:
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return -1;
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}
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}
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default:
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return -1;
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}
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}
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case 24:
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{
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switch ((op.encoding >> 23) & 0x7) {
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// vadd, vsub, vdiv
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case 0:
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case 1:
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case 7:
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MIPSInt::Int_VecDo3(mips, op);
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return 2;
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// vsbn
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case 2:
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MIPSInt::Int_Vsbn(mips, op);
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return 2;
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default:
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return -1;
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}
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}
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case 25:
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{
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switch ((op.encoding >> 23) & 0x7) {
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// vmul
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case 0:
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MIPSInt::Int_VecDo3(mips, op);
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return 2;
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// vdot
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case 1:
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MIPSInt::Int_VDot(mips, op);
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return 2;
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// vscl
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case 2:
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MIPSInt::Int_VScl(mips, op);
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return 2;
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// vhdp
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case 4:
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MIPSInt::Int_VHdp(mips, op);
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return 2;
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// vcrs
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case 5:
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MIPSInt::Int_Vcrs(mips, op);
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return 2;
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// vdet
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case 6:
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MIPSInt::Int_Vdet(mips, op);
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return 2;
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default:
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return -1;
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}
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}
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case 26:
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{
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switch ((op.encoding >> 24) & 0x3) {
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// CallRepl
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case 2:
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MIPSInt::Int_CallReplacement(mips, op);
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return 1;
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default:
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return -1;
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}
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}
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case 27:
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{
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switch ((op.encoding >> 23) & 0x7) {
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// vcmp
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case 0:
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MIPSInt::Int_Vcmp(mips, op);
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return 2;
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// vmin, vmax
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case 2:
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case 3:
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MIPSInt::Int_Vminmax(mips, op);
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return 2;
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// vscmp
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case 5:
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MIPSInt::Int_Vscmp(mips, op);
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return 2;
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// vsge
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case 6:
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MIPSInt::Int_Vsge(mips, op);
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return 2;
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// vslt
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case 7:
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MIPSInt::Int_Vslt(mips, op);
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return 2;
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default:
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return -1;
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}
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}
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case 28:
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{
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switch ((op.encoding >> 0) & 0x3f) {
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// mfic, mtic
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case 36:
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case 38:
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MIPSInt::Int_Special2(mips, op);
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return 1;
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default:
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return -1;
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}
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}
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case 31:
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{
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switch ((op.encoding >> 0) & 0x3f) {
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// ext, ins
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case 0:
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case 4:
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MIPSInt::Int_Special3(mips, op);
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return 1;
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// nop
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case 24:
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MIPSInt::Int_Sync(mips, op);
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return 1;
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case 32:
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{
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switch ((op.encoding >> 6) & 0x1f) {
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// wsbh, wsbw
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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case 6:
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case 7:
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case 8:
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case 9:
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case 10:
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case 11:
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case 12:
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case 13:
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case 14:
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case 15:
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MIPSInt::Int_Allegrex2(mips, op);
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return 1;
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// seb, bitrev, seh
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case 16:
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case 17:
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case 18:
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case 19:
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case 20:
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case 21:
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case 22:
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case 23:
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case 24:
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case 25:
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case 26:
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case 27:
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case 28:
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case 29:
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case 30:
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case 31:
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MIPSInt::Int_Allegrex(mips, op);
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return 1;
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default:
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return -1;
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}
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}
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default:
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return -1;
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}
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}
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// lb, lh, lwl, lw, lbu, lhu, lwr, sb, sh, swl, sw, swr
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case 32:
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case 33:
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case 34:
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case 35:
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case 36:
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case 37:
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case 38:
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case 40:
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case 41:
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case 42:
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case 43:
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case 46:
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MIPSInt::Int_ITypeMem(mips, op);
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return 1;
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// cache
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case 47:
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MIPSInt::Int_Cache(mips, op);
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return 1;
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// ll, sc
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case 48:
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case 56:
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MIPSInt::Int_StoreSync(mips, op);
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return 1;
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// lwc1, swc1
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case 49:
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case 57:
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MIPSInt::Int_FPULS(mips, op);
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return 1;
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// lv.s, sv.s
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case 50:
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case 58:
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MIPSInt::Int_SV(mips, op);
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return 2;
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case 52:
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{
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switch ((op.encoding >> 21) & 0x1f) {
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case 0:
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{
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switch ((op.encoding >> 16) & 0x1f) {
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// vmov, vabs, vneg, vsat0, vsat1, vrcp, vrsq, vsin, vcos, vexp2, vlog2, vsqrt, vasin, vnrcp, vnsin, vrexp2
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case 0:
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case 1:
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case 2:
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case 4:
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case 5:
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case 16:
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case 17:
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case 18:
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case 19:
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case 20:
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case 21:
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case 22:
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case 23:
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case 24:
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case 26:
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case 28:
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MIPSInt::Int_VV2Op(mips, op);
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return 2;
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// vidt
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case 3:
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MIPSInt::Int_Vidt(mips, op);
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return 2;
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// vzero, vone
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case 6:
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case 7:
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MIPSInt::Int_VVectorInit(mips, op);
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return 2;
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default:
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return -1;
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}
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}
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case 1:
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{
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switch ((op.encoding >> 16) & 0x1f) {
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// vrnds
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case 0:
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MIPSInt::Int_Vrnds(mips, op);
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return 2;
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// vrndi, vrndf1, vrndf2
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case 1:
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case 2:
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case 3:
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MIPSInt::Int_VrndX(mips, op);
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return 2;
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// vf2h
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case 18:
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MIPSInt::Int_Vf2h(mips, op);
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return 2;
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// vh2f
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case 19:
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MIPSInt::Int_Vh2f(mips, op);
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return 2;
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// vsbz
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case 22:
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MIPSInt::Int_Vsbz(mips, op);
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return 2;
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// vlgb
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case 23:
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MIPSInt::Int_Vlgb(mips, op);
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return 2;
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// vuc2ifs, vc2i, vus2i, vs2i
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case 24:
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case 25:
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case 26:
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case 27:
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MIPSInt::Int_Vx2i(mips, op);
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return 2;
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// vi2uc, vi2c, vi2us, vi2s
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case 28:
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case 29:
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case 30:
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case 31:
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MIPSInt::Int_Vi2x(mips, op);
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return 2;
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default:
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return -1;
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}
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}
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case 2:
|
|
{
|
|
switch ((op.encoding >> 16) & 0x1f) {
|
|
// vsrt1
|
|
case 0:
|
|
MIPSInt::Int_Vsrt1(mips, op);
|
|
return 2;
|
|
// vsrt2
|
|
case 1:
|
|
MIPSInt::Int_Vsrt2(mips, op);
|
|
return 2;
|
|
// vbfy1, vbfy2
|
|
case 2:
|
|
case 3:
|
|
MIPSInt::Int_Vbfy(mips, op);
|
|
return 2;
|
|
// vocp
|
|
case 4:
|
|
MIPSInt::Int_Vocp(mips, op);
|
|
return 2;
|
|
// vsocp
|
|
case 5:
|
|
MIPSInt::Int_Vsocp(mips, op);
|
|
return 2;
|
|
// vfad
|
|
case 6:
|
|
MIPSInt::Int_Vfad(mips, op);
|
|
return 2;
|
|
// vavg
|
|
case 7:
|
|
MIPSInt::Int_Vavg(mips, op);
|
|
return 2;
|
|
// vsrt3
|
|
case 8:
|
|
MIPSInt::Int_Vsrt3(mips, op);
|
|
return 2;
|
|
// vsrt4
|
|
case 9:
|
|
MIPSInt::Int_Vsrt4(mips, op);
|
|
return 2;
|
|
// vsgn
|
|
case 10:
|
|
MIPSInt::Int_Vsgn(mips, op);
|
|
return 2;
|
|
// vmfvc
|
|
case 16:
|
|
MIPSInt::Int_Vmfvc(mips, op);
|
|
return 2;
|
|
// vmtvc
|
|
case 17:
|
|
MIPSInt::Int_Vmtvc(mips, op);
|
|
return 2;
|
|
// vt4444, vt5551, vt5650
|
|
case 25:
|
|
case 26:
|
|
case 27:
|
|
MIPSInt::Int_ColorConv(mips, op);
|
|
return 2;
|
|
default:
|
|
return -1;
|
|
}
|
|
}
|
|
// vcst
|
|
case 3:
|
|
MIPSInt::Int_Vcst(mips, op);
|
|
return 2;
|
|
// vf2in, vf2iz, vf2iu, vf2id
|
|
case 16:
|
|
case 17:
|
|
case 18:
|
|
case 19:
|
|
MIPSInt::Int_Vf2i(mips, op);
|
|
return 2;
|
|
// vi2f
|
|
case 20:
|
|
MIPSInt::Int_Vi2f(mips, op);
|
|
return 2;
|
|
// vcmov
|
|
case 21:
|
|
MIPSInt::Int_Vcmov(mips, op);
|
|
return 2;
|
|
// vwbn
|
|
case 24:
|
|
case 25:
|
|
case 26:
|
|
case 27:
|
|
case 28:
|
|
case 29:
|
|
case 30:
|
|
case 31:
|
|
MIPSInt::Int_Vwbn(mips, op);
|
|
return 2;
|
|
default:
|
|
return -1;
|
|
}
|
|
}
|
|
// lv, lv.q, sv, sv.q
|
|
case 53:
|
|
case 54:
|
|
case 61:
|
|
case 62:
|
|
MIPSInt::Int_SVQ(mips, op);
|
|
return 2;
|
|
case 55:
|
|
{
|
|
switch ((op.encoding >> 23) & 0x7) {
|
|
// vpfxs, vpfxt, vpfxd
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
case 4:
|
|
case 5:
|
|
MIPSInt::Int_VPFX(mips, op);
|
|
return 2;
|
|
// viim.s, vfim.s
|
|
case 6:
|
|
case 7:
|
|
MIPSInt::Int_Viim(mips, op);
|
|
return 2;
|
|
default:
|
|
return -1;
|
|
}
|
|
}
|
|
case 60:
|
|
{
|
|
switch ((op.encoding >> 21) & 0x1f) {
|
|
// vmmul
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
MIPSInt::Int_Vmmul(mips, op);
|
|
return 2;
|
|
// v(h)tfm2, v(h)tfm3, v(h)tfm4
|
|
case 4:
|
|
case 5:
|
|
case 6:
|
|
case 7:
|
|
case 8:
|
|
case 9:
|
|
case 10:
|
|
case 11:
|
|
case 12:
|
|
case 13:
|
|
case 14:
|
|
case 15:
|
|
MIPSInt::Int_Vtfm(mips, op);
|
|
return 2;
|
|
// vmscl
|
|
case 16:
|
|
case 17:
|
|
case 18:
|
|
case 19:
|
|
MIPSInt::Int_Vmscl(mips, op);
|
|
return 2;
|
|
// vcrsp.t/vqmul.q
|
|
case 20:
|
|
case 21:
|
|
case 22:
|
|
case 23:
|
|
MIPSInt::Int_CrossQuat(mips, op);
|
|
return 2;
|
|
case 28:
|
|
{
|
|
switch ((op.encoding >> 16) & 0xf) {
|
|
// vmmov
|
|
case 0:
|
|
MIPSInt::Int_Vmmov(mips, op);
|
|
return 2;
|
|
// vmidt, vmzero, vmone
|
|
case 3:
|
|
case 6:
|
|
case 7:
|
|
MIPSInt::Int_VMatrixInit(mips, op);
|
|
return 2;
|
|
default:
|
|
return -1;
|
|
}
|
|
}
|
|
// vrot
|
|
case 29:
|
|
MIPSInt::Int_Vrot(mips, op);
|
|
return 2;
|
|
default:
|
|
return -1;
|
|
}
|
|
}
|
|
// vflush
|
|
case 63:
|
|
MIPSInt::Int_Vflush(mips, op);
|
|
return 2;
|
|
default:
|
|
return -1;
|
|
}
|
|
}
|