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All ~82 MIPSInt::Int_* functions (Interpreter.cpp/.h, InterpreterVFPU.cpp/.h) now take an explicit MIPSState *mips instead of reaching for the global currentMIPS internally, along with their file-local helpers (DelayBranchTo, SkipLikely, ApplySwizzleS/T, ApplyPrefixD/ST, RetainInvalidSwizzleST, EatPrefixes). MIPSInterpretFunc, Interpret(), ExecInstruction()/InterpreterDispatch.cpp (regenerated), and RunUntilFast() all thread mips through accordingly. Deliberately left on currentMIPS for now: MIPSVFPUUtils.cpp's ReadVector/WriteVector/ReadMatrix/WriteMatrix/VFPURewritePrefix - these are shared with every JIT backend's compile-time VFPU code, so parameterizing them would balloon this into a JIT-wide refactor. This is a partial refactor; that's the next boundary to push on. Several JIT backends (x86 Jit.cpp, ARM/ArmJit.cpp, ARM64/Arm64Jit.cpp, x86/X64IRJit.cpp, RiscV/RiscVJit.cpp, LoongArch64/LoongArch64Jit.cpp, ARM64/Arm64IRJit.cpp) bake the raw interpreter function pointer directly into JIT-generated machine code as their "fall back to the interpreter for this one op" mechanism, with only a single argument register set up for the call. Rather than hand-editing register allocation across four architectures that can't be build-tested here, added MIPSInterpretTrampoline(MIPSOpcode op) - a 1-arg wrapper around MIPSInterpret(currentMIPS, op) - and pointed all 7 such call sites at it instead, leaving that codegen untouched. Two other call sites (JitLogMiss, JitBranchLog) were plain C++ calls and just got the extra argument directly. Verified (Windows x64): PPSSPPWindows/PPSSPPHeadless/UnitTest all build clean, 49/49 unit tests pass. `test.py -g --graphics=software`: interpreter 312/314 (cpu/fpu/fpu is the pre-existing, unrelated interpreter-vs-JIT denormal difference; gpu/rendertarget/copy passes standalone, so was cross-test state bleed in the batch run, not a regression), default JIT 314/314, jit-ir 313/314 (gpu/vertices/morph is an expected difference from the vertex decoder taking a different mode with this core change, not a bug). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_019SKhm9wKEQzRUsx9mTrrtQ
155 lines
5.1 KiB
C++
155 lines
5.1 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include <string>
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#include <cstdint>
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#include "Common/CommonTypes.h"
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#include "Core/MIPS/MIPS.h"
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#define CONDTYPE_MASK 0x00000007
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#define CONDTYPE_EQ 0x00000001
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#define CONDTYPE_NE 0x00000002
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#define CONDTYPE_LEZ 0x00000003
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#define CONDTYPE_GTZ 0x00000004
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#define CONDTYPE_LTZ 0x00000005
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#define CONDTYPE_GEZ 0x00000006
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#define CONDTYPE_FPUFALSE CONDTYPE_EQ
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#define CONDTYPE_FPUTRUE CONDTYPE_NE
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// as long as the other flags are checked,
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// there is no way to misinterpret these
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// as CONDTYPE_X
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#define MEMTYPE_MASK 0x00000007ULL
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#define MEMTYPE_BYTE 0x00000001ULL
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#define MEMTYPE_HWORD 0x00000002ULL
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#define MEMTYPE_WORD 0x00000003ULL
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#define MEMTYPE_FLOAT 0x00000004ULL
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#define MEMTYPE_VQUAD 0x00000005ULL
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#define IS_CONDMOVE 0x00000008ULL
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#define DELAYSLOT 0x00000010ULL
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#define BAD_INSTRUCTION 0x00000020ULL
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#define LIKELY 0x00000040ULL
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#define IS_CONDBRANCH 0x00000080ULL
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#define IS_JUMP 0x00000100ULL
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#define IN_RS 0x00000200ULL
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#define IN_RS_ADDR (0x00000400ULL | IN_RS)
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#define IN_RS_SHIFT (0x00000800ULL | IN_RS)
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#define IN_RT 0x00001000ULL
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#define IN_SA 0x00002000ULL
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#define IN_IMM16 0x00004000ULL
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#define IN_IMM26 0x00008000ULL
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#define IN_MEM 0x00010000ULL
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#define IN_OTHER 0x00020000ULL
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#define IN_FPUFLAG 0x00040000ULL
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#define IN_VFPU_CC 0x00080000ULL
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#define OUT_RT 0x00100000ULL
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#define OUT_RD 0x00200000ULL
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#define OUT_RA 0x00400000ULL
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#define OUT_MEM 0x00800000ULL
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#define OUT_OTHER 0x01000000ULL
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#define OUT_FPUFLAG 0x02000000ULL
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#define OUT_VFPU_CC 0x04000000ULL
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#define OUT_EAT_PREFIX 0x08000000ULL
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#define VFPU_NO_PREFIX 0x10000000ULL
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#define OUT_VFPU_PREFIX 0x20000000ULL
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#define IS_VFPU 0x40000000ULL
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#define IS_FPU 0x80000000ULL
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#define IN_FS 0x000100000000ULL
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#define IN_FT 0x000200000000ULL
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#define IN_LO 0x000400000000ULL
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#define IN_HI 0x000800000000ULL
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#define OUT_FD 0x001000000000ULL
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#define OUT_FS 0x002000000000ULL
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#define OUT_LO 0x004000000000ULL
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#define OUT_HI 0x008000000000ULL
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#define IN_VS 0x010000000000ULL
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#define IN_VT 0x020000000000ULL
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#define OUT_FT 0x040000000000ULL
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#define OUT_VD 0x100000000000ULL
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#define IS_SYSCALL 0x200000000000ULL
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#ifndef CDECL
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#define CDECL
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#endif
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struct MIPSInfo {
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MIPSInfo() {
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value = 0;
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cycles = 0;
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}
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explicit MIPSInfo(u64 v, u16 c = 0) : value(v), cycles(c) {
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if (c == 0) {
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cycles = 1;
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if (v & IS_VFPU)
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cycles++;
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}
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}
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u64 operator & (const u64 &arg) const {
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return value & arg;
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}
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u64 value : 48;
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u64 cycles : 16;
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};
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typedef void (CDECL *MIPSDisFunc)(MIPSOpcode opcode, uint32_t pc, char *out, size_t outSize);
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typedef void (CDECL *MIPSInterpretFunc)(MIPSState *mips, MIPSOpcode opcode);
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namespace MIPSComp {
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class MIPSFrontendInterface;
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}
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void MIPSCompileOp(MIPSOpcode op, MIPSComp::MIPSFrontendInterface *jit);
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void MIPSDisAsm(MIPSOpcode op, u32 pc, char *out, size_t outSize, bool tabsToSpaces = false);
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MIPSInfo MIPSGetInfo(MIPSOpcode op);
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void MIPSInterpret(MIPSState *mips, MIPSOpcode op); //only for those rare ones
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int MIPSInterpret_RunUntil(MIPSState *mips, u64 globalTicks);
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MIPSInterpretFunc MIPSGetInterpretFunc(MIPSOpcode op);
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// 1-arg (MIPSOpcode only) trampoline around MIPSInterpret(currentMIPS, op), for JIT backends
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// (x86/ARM/ARM64/RiscV/LoongArch64 Comp_Generic / CompIR_Interpret) that bake a raw function
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// pointer directly into generated machine code as their interpreter fallback - that codegen
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// only arranges a single MIPSOpcode argument before the call, so it can't target a real
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// MIPSInterpretFunc (now 2-arg) without also being taught to pass an explicit MIPSState*.
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// TODO: teach each JIT's codegen to pass mips explicitly, then delete this.
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void CDECL MIPSInterpretTrampoline(MIPSOpcode op);
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int MIPSGetInstructionCycleEstimate(MIPSOpcode op);
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int MIPSGetMemoryAccessSize(MIPSOpcode op);
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const char *MIPSGetName(MIPSOpcode op);
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std::string MIPSDisasmAt(u32 compilerPC);
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// Generates the full contents of Core/MIPS/InterpreterDispatch.cpp: a fast switch-tree
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// int ExecInstruction(MIPSState *mips, MIPSOpcode op) dispatcher, derived from the tables in
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// MIPSTables.cpp. See GenerateInterpreterDispatch()'s comment (in the .cpp) for details.
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std::string GenerateInterpreterDispatch();
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