None of these are reachable from current JIT code with the registers it
uses, but they emit wrong or unallocated instructions:
- EXTR put Rm in the Rn field.
- CRC32X/CRC32CX took sf from the W destination (unallocated encoding).
- LDRSB/LDRSH/LDRSW (immediate) with an X destination set the size bits
again, turning them into other loads or prfm.
- LDPSW encoded opc 11 (unallocated) and scaled the offset by 8.
- CMxx and LD1R/LD2R with 64-bit elements used size >> 4, which spills
out of the size field. The CMxx asserts were inverted too.
- SCVTF/UCVTF between FP registers always encoded the single version.
- FCVTZS/FCVTZU to a GPR with a scale wrote fbits into the scale field,
which holds 64 - fbits.
- LDURSW asserted a 32-bit destination.
- CLREX now uses the canonical CRm of 15.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
