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https://github.com/hrydgard/ppsspp.git
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Henrik RydgårdandClaude Opus 5.5
66d7975e7f
Their IR-based replacements stay. The JIT core now creates the IR JIT on both, so "JIT using IR" is the same as "JIT" on every architecture (ARM32 still uses its legacy JIT for both). The settings no longer offer it, a saved JIT_IR loads as JIT, and the JIT harness and CPUEquivalence fuzzer drop the duplicate run. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
138 lines
4.6 KiB
C++
138 lines
4.6 KiB
C++
#include "ppsspp_config.h"
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#if PPSSPP_ARCH(AMD64) || PPSSPP_ARCH(X86)
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#include "Common/CPUDetect.h"
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#include "Common/x64Analyzer.h"
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#include "Common/x64Emitter.h"
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#include "Core/MIPS/JitCommon/JitState.h"
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#include "Core/MIPS/JitCommon/JitCommon.h"
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#include "Core/MIPS/MIPSVFPUUtils.h"
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#include "ext/disarm.h"
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#include "UnitTest.h"
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static const u8 *prevStart = NULL;
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static bool CheckLast(const Gen::XEmitter &emit, const char *comp) {
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auto vec = DisassembleX86(prevStart, (int)(emit.GetCodePointer() - prevStart));
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EXPECT_EQ_STR(vec[0], std::string(comp));
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return true;
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}
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// Emits nothing itself - runs the x64 crash-handler instruction analyzer (Common/x64Analyzer.cpp)
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// on the instruction most recently emitted (from prevStart to the emitter's current position),
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// and checks that it decoded it the way we expect.
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static bool CheckAnalyze(const Gen::XEmitter &emit, bool expectWrite, InstructionClass expectClass, int expectOperandSize, bool expectZeroExtend = false, bool expectSignExtend = false) {
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LSInstructionInfo info{};
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bool success = X86AnalyzeMOV(prevStart, info);
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EXPECT_TRUE(success);
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EXPECT_EQ_INT(info.instructionSize, (int)(emit.GetCodePointer() - prevStart));
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EXPECT_EQ_INT(info.isMemoryWrite, expectWrite);
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EXPECT_EQ_INT((int)info.instructionClass, (int)expectClass);
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EXPECT_EQ_INT(info.operandSizeInBytes, expectOperandSize);
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EXPECT_EQ_INT(info.zeroExtend, expectZeroExtend);
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EXPECT_EQ_INT(info.signExtend, expectSignExtend);
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return true;
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}
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static void PrintLast(const Gen::XEmitter &emit) {
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for (const u8 *p = prevStart; p < emit.GetCodePointer(); p++) {
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printf("%02x ", *p);
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}
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printf("\n");
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}
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bool TestX64Emitter() {
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using namespace Gen;
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u32 code[512];
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XEmitter emitter((u8 *)code);
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bool prevAVX = cpu_info.bAVX;
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cpu_info.bAVX = true;
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prevStart = emitter.GetCodePointer();
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emitter.VADDSD(XMM0, XMM1, R(XMM7));
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RET(CheckLast(emitter, "vaddsd xmm0, xmm1, xmm7"));
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prevStart = emitter.GetCodePointer();
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emitter.VMULSD(XMM0, XMM1, R(XMM7));
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RET(CheckLast(emitter, "vmulsd xmm0, xmm1, xmm7"));
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cpu_info.bAVX = prevAVX;
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// Exercise Common/x64Analyzer.cpp (used by the JIT crash handler to figure out what a faulting
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// load/store instruction was doing) against instructions written by the emitter, for the most
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// common memory access instructions.
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prevStart = emitter.GetCodePointer();
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emitter.MOV(32, R(EAX), MDisp(RCX, 4));
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RET(CheckAnalyze(emitter, false, InstructionClass::GPR, 4));
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prevStart = emitter.GetCodePointer();
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emitter.MOV(32, MDisp(RCX, 4), R(EAX));
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RET(CheckAnalyze(emitter, true, InstructionClass::GPR, 4));
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// The 8-bit forms, which the JIT emits for a guest sb/lb. These used to fail to decode
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// entirely, so MemFault couldn't skip or ignore a bad byte access the way it can a word one.
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prevStart = emitter.GetCodePointer();
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emitter.MOV(8, MDisp(RCX, 4), R(AL));
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RET(CheckAnalyze(emitter, true, InstructionClass::GPR, 1));
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prevStart = emitter.GetCodePointer();
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emitter.MOV(8, R(AL), MDisp(RCX, 4));
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RET(CheckAnalyze(emitter, false, InstructionClass::GPR, 1));
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prevStart = emitter.GetCodePointer();
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emitter.MOVZX(32, 8, EAX, MDisp(RCX, 4));
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RET(CheckAnalyze(emitter, false, InstructionClass::GPR, 1, true, false));
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prevStart = emitter.GetCodePointer();
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emitter.MOVZX(32, 16, EAX, MDisp(RCX, 4));
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RET(CheckAnalyze(emitter, false, InstructionClass::GPR, 2, true, false));
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prevStart = emitter.GetCodePointer();
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emitter.MOVSX(32, 8, EAX, MDisp(RCX, 4));
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RET(CheckAnalyze(emitter, false, InstructionClass::GPR, 1, false, true));
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prevStart = emitter.GetCodePointer();
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emitter.MOVSX(32, 16, EAX, MDisp(RCX, 4));
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RET(CheckAnalyze(emitter, false, InstructionClass::GPR, 2, false, true));
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prevStart = emitter.GetCodePointer();
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emitter.MOVSS(XMM0, MDisp(RCX, 4));
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RET(CheckAnalyze(emitter, false, InstructionClass::FP, 4));
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prevStart = emitter.GetCodePointer();
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emitter.MOVSS(MDisp(RCX, 4), XMM0);
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RET(CheckAnalyze(emitter, true, InstructionClass::FP, 4));
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prevStart = emitter.GetCodePointer();
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emitter.MOVUPS(XMM0, MDisp(RCX, 4));
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RET(CheckAnalyze(emitter, false, InstructionClass::FP_SIMD, 16));
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prevStart = emitter.GetCodePointer();
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emitter.MOVUPS(MDisp(RCX, 4), XMM0);
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RET(CheckAnalyze(emitter, true, InstructionClass::FP_SIMD, 16));
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prevStart = emitter.GetCodePointer();
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emitter.MOVAPS(XMM0, MDisp(RCX, 4));
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RET(CheckAnalyze(emitter, false, InstructionClass::FP_SIMD, 16));
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prevStart = emitter.GetCodePointer();
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emitter.MOVAPS(MDisp(RCX, 4), XMM0);
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RET(CheckAnalyze(emitter, true, InstructionClass::FP_SIMD, 16));
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// Just for checking.
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PrintLast(emitter);
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return true;
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}
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#else
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bool TestX64Emitter() {
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return true;
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}
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#endif
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