mirror of
https://github.com/hrydgard/ppsspp.git
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252 lines
7.7 KiB
C++
252 lines
7.7 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Core/Config.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSAnalyst.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/IR/IRFrontend.h"
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#include "Core/MIPS/IR/IRRegCache.h"
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE ;
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#define DISABLE { Comp_Generic(op); return; }
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#define INVALIDOP { Comp_Generic(op); return; }
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namespace MIPSComp {
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void IRFrontend::Comp_ITypeMemLR(MIPSOpcode op, bool load) {
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CONDITIONAL_DISABLE;
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int offset = _IMM16;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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int o = op >> 26;
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if (!js.inDelaySlot && opts.unalignedLoadStore) {
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// Optimisation: Combine to single unaligned load/store.
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const bool isLeft = (o == 34 || o == 42);
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MIPSOpcode nextOp = GetOffsetInstruction(1);
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// Find a matching shifted load/store in opposite direction with opposite offset.
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if (nextOp == (isLeft ? (op.encoding + (4 << 26) - 3) : (op.encoding - (4 << 26) + 3))) {
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EatInstruction(nextOp);
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if (isLeft) {
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// Get the unaligned base offset from the lwr/swr instruction.
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offset = (signed short)(nextOp & 0xFFFF);
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// Already checked it if we're on the lwr.
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CheckMemoryBreakpoint(rs, offset);
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}
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if (load) {
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ir.Write(IROp::Load32, rt, rs, ir.AddConstant(offset));
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} else {
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ir.Write(IROp::Store32, rt, rs, ir.AddConstant(offset));
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}
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return;
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}
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}
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int addrReg = IRTEMP_0;
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int valueReg = IRTEMP_1;
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int maskReg = IRTEMP_2;
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int shiftReg = IRTEMP_3;
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// addrReg = rs + imm
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ir.Write(IROp::AddConst, addrReg, rs, ir.AddConstant(offset));
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// shiftReg = (addr & 3) * 8
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ir.Write(IROp::AndConst, shiftReg, addrReg, ir.AddConstant(3));
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ir.Write(IROp::ShlImm, shiftReg, shiftReg, 3);
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// addrReg = addr & 0xfffffffc (for stores, later)
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ir.Write(IROp::AndConst, addrReg, addrReg, ir.AddConstant(0xFFFFFFFC));
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// valueReg = RAM(addrReg)
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ir.Write(IROp::Load32, valueReg, addrReg, ir.AddConstant(0));
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switch (o) {
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case 34: //lwl
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// rt &= (0x00ffffff >> shift)
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// Alternatively, could shift to a wall and back (but would require two shifts each way.)
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ir.WriteSetConstant(maskReg, 0x00ffffff);
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ir.Write(IROp::Shr, maskReg, maskReg, shiftReg);
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ir.Write(IROp::And, rt, rt, maskReg);
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// valueReg <<= (24 - shift)
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ir.Write(IROp::Neg, shiftReg, shiftReg);
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ir.Write(IROp::AddConst, shiftReg, shiftReg, ir.AddConstant(24));
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ir.Write(IROp::Shl, valueReg, valueReg, shiftReg);
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// rt |= valueReg
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ir.Write(IROp::Or, rt, rt, valueReg);
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break;
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case 38: //lwr
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// valueReg >>= shift
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ir.Write(IROp::Shr, valueReg, valueReg, shiftReg);
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// shiftReg = 24 - shift
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ir.Write(IROp::Neg, shiftReg, shiftReg);
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ir.Write(IROp::AddConst, shiftReg, shiftReg, ir.AddConstant(24));
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// rt &= (0xffffff00 << (24 - shift))
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// Alternatively, could shift to a wall and back (but would require two shifts each way.)
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ir.WriteSetConstant(maskReg, 0xffffff00);
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ir.Write(IROp::Shl, maskReg, maskReg, shiftReg);
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ir.Write(IROp::And, rt, rt, maskReg);
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// rt |= valueReg
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ir.Write(IROp::Or, rt, rt, valueReg);
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break;
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case 42: //swl
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// valueReg &= 0xffffff00 << shift
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ir.WriteSetConstant(maskReg, 0xffffff00);
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ir.Write(IROp::Shl, maskReg, maskReg, shiftReg);
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ir.Write(IROp::And, valueReg, valueReg, maskReg);
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// shiftReg = 24 - shift
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ir.Write(IROp::Neg, shiftReg, shiftReg);
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ir.Write(IROp::AddConst, shiftReg, shiftReg, ir.AddConstant(24));
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// valueReg |= rt >> (24 - shift)
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ir.Write(IROp::Shr, maskReg, rt, shiftReg);
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ir.Write(IROp::Or, valueReg, valueReg, maskReg);
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break;
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case 46: //swr
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// valueReg &= 0x00ffffff << (24 - shift)
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ir.WriteSetConstant(maskReg, 0x00ffffff);
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ir.Write(IROp::Neg, shiftReg, shiftReg);
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ir.Write(IROp::AddConst, shiftReg, shiftReg, ir.AddConstant(24));
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ir.Write(IROp::Shl, maskReg, maskReg, shiftReg);
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ir.Write(IROp::And, valueReg, valueReg, maskReg);
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ir.Write(IROp::Neg, shiftReg, shiftReg);
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ir.Write(IROp::AddConst, shiftReg, shiftReg, ir.AddConstant(24));
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// valueReg |= rt << shift
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ir.Write(IROp::Shl, maskReg, rt, shiftReg);
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ir.Write(IROp::Or, valueReg, valueReg, maskReg);
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break;
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default:
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INVALIDOP;
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return;
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}
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if (!load) {
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// RAM(addrReg) = valueReg
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ir.Write(IROp::Store32, valueReg, addrReg, ir.AddConstant(0));
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}
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}
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void IRFrontend::Comp_ITypeMem(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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int offset = _IMM16;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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int o = op >> 26;
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if (((op >> 29) & 1) == 0 && rt == MIPS_REG_ZERO) {
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// Don't load anything into $zr
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return;
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}
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CheckMemoryBreakpoint(rs, offset);
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switch (o) {
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// Load
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case 35:
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ir.Write(IROp::Load32, rt, rs, ir.AddConstant(offset));
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break;
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case 37:
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ir.Write(IROp::Load16, rt, rs, ir.AddConstant(offset));
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break;
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case 33:
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ir.Write(IROp::Load16Ext, rt, rs, ir.AddConstant(offset));
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break;
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case 36:
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ir.Write(IROp::Load8, rt, rs, ir.AddConstant(offset));
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break;
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case 32:
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ir.Write(IROp::Load8Ext, rt, rs, ir.AddConstant(offset));
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break;
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// Store
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case 43:
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ir.Write(IROp::Store32, rt, rs, ir.AddConstant(offset));
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break;
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case 41:
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ir.Write(IROp::Store16, rt, rs, ir.AddConstant(offset));
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break;
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case 40:
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ir.Write(IROp::Store8, rt, rs, ir.AddConstant(offset));
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break;
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case 34: //lwl
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case 38: //lwr
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Comp_ITypeMemLR(op, true);
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break;
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case 42: //swl
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case 46: //swr
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Comp_ITypeMemLR(op, false);
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break;
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default:
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INVALIDOP;
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return;
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}
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}
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void IRFrontend::Comp_Cache(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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// int imm = (s16)(op & 0xFFFF);
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// int rs = _RS;
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// int addr = R(rs) + imm;
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int func = (op >> 16) & 0x1F;
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// It appears that a cache line is 0x40 (64) bytes, loops in games
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// issue the cache instruction at that interval.
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// These codes might be PSP-specific, they don't match regular MIPS cache codes very well
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switch (func) {
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// Icache
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case 8:
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// Invalidate the instruction cache at this address
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DISABLE;
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break;
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// Dcache
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case 24:
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// "Create Dirty Exclusive" - for avoiding a cacheline fill before writing to it.
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// Will cause garbage on the real machine so we just ignore it, the app will overwrite the cacheline.
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break;
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case 25: // Hit Invalidate - zaps the line if present in cache. Should not writeback???? scary.
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// No need to do anything.
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break;
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case 27: // D-cube. Hit Writeback Invalidate. Tony Hawk Underground 2
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break;
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case 30: // GTA LCS, a lot. Fill (prefetch). Tony Hawk Underground 2
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break;
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default:
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DISABLE;
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break;
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}
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}
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}
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