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Henrik RydgårdandClaude Opus 5.5
f7db56628c
The old disarm handled the integer instructions but only a fraction of VFP and NEON, and got several of those wrong. The new one decodes ARMv7-A ARM state with VFPv4 and NEON, printing UAL with upper case mnemonics. The new ArmDisasm test runs every ARM emitter function through it, two examples each. Tools/arm_disasm_check.py compares the test's output with llvm-mc; they agree on all of it. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
47 lines
1.4 KiB
C++
47 lines
1.4 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include <cstdint>
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// ARMv7-A disassembler for ARM state, including VFP and NEON.
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const char *ArmRegName(int r);
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void ArmDis(unsigned int addr, unsigned int w, char *output, int bufsize, bool includeWord);
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// Information about a load/store instruction.
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struct ArmLSInstructionInfo {
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int instructionSize;
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bool isIntegerLoadStore;
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bool isFPLoadStore;
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bool isMultiLoadStore;
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int size; // 0 = 8-bit, 1 = 16-bit, 2 = 32-bit, 3 = 64-bit
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bool isMemoryWrite;
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int Rt;
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int Rn;
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int Rm;
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// TODO: more.
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int OperandSizeInBytes() const { return 1 << size; }
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};
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bool ArmAnalyzeLoadStore(uint32_t addr, uint32_t op, ArmLSInstructionInfo *info);
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