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https://github.com/hrydgard/ppsspp.git
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Sacha
583927988c
Implement vsat0 and vsat1 Introduce VMOV for immediates. Use in MOVI2F where possible by detecting if float val can be encoded. Combine some vneg ops in ApplyPrefixST.
358 lines
8.9 KiB
C++
358 lines
8.9 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Core/Config.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "ArmJit.h"
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#include "ArmRegCache.h"
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#define _RS ((op>>21) & 0x1F)
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#define _RT ((op>>16) & 0x1F)
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#define _RD ((op>>11) & 0x1F)
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#define _FS ((op>>11) & 0x1F)
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#define _FT ((op>>16) & 0x1F)
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#define _FD ((op>>6 ) & 0x1F)
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#define _POS ((op>>6 ) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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//#define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE ;
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#define DISABLE { Comp_Generic(op); return; }
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namespace MIPSComp
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{
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void Jit::Comp_FPU3op(u32 op)
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{
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CONDITIONAL_DISABLE;
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int ft = _FT;
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int fs = _FS;
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int fd = _FD;
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fpr.MapDirtyInIn(fd, fs, ft);
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switch (op & 0x3f)
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{
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case 0: VADD(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) + F(ft); //add
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case 1: VSUB(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) - F(ft); //sub
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case 2: { //F(fd) = F(fs) * F(ft); //mul
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u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4);
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// Optimise possible if destination is the same
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if (fd == ((nextOp>>6) & 0x1F)) {
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// VMUL + VNEG -> VNMUL
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if (!strcmp(MIPSGetName(nextOp), "neg.s")) {
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if (fd == ((nextOp>>11) & 0x1F)) {
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VNMUL(fpr.R(fd), fpr.R(fs), fpr.R(ft));
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EatInstruction(nextOp);
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}
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return;
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}
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}
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VMUL(fpr.R(fd), fpr.R(fs), fpr.R(ft));
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break;
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}
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case 3: VDIV(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) / F(ft); //div
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default:
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DISABLE;
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return;
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}
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}
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extern int logBlocks;
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void Jit::Comp_FPULS(u32 op)
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{
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CONDITIONAL_DISABLE;
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s32 offset = (s16)(op & 0xFFFF);
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int ft = _FT;
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int rs = _RS;
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// u32 addr = R(rs) + offset;
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// logBlocks = 1;
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bool doCheck = false;
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switch(op >> 26)
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{
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case 49: //FI(ft) = Memory::Read_U32(addr); break; //lwc1
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fpr.MapReg(ft, MAP_NOINIT | MAP_DIRTY);
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if (gpr.IsImm(rs)) {
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u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
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MOVI2R(R0, addr + (u32)Memory::base);
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} else {
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gpr.MapReg(rs);
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if (g_Config.bFastMemory) {
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SetR0ToEffectiveAddress(rs, offset);
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} else {
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SetCCAndR0ForSafeAddress(rs, offset, R1);
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doCheck = true;
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}
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ADD(R0, R0, R11);
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}
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VLDR(fpr.R(ft), R0, 0);
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if (doCheck) {
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SetCC(CC_EQ);
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MOVI2R(R0, 0);
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VMOV(fpr.R(ft), R0);
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SetCC(CC_AL);
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}
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break;
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case 57: //Memory::Write_U32(FI(ft), addr); break; //swc1
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fpr.MapReg(ft);
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if (gpr.IsImm(rs)) {
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u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
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MOVI2R(R0, addr + (u32)Memory::base);
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} else {
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gpr.MapReg(rs);
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if (g_Config.bFastMemory) {
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SetR0ToEffectiveAddress(rs, offset);
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} else {
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SetCCAndR0ForSafeAddress(rs, offset, R1);
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doCheck = true;
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}
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ADD(R0, R0, R11);
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}
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VSTR(fpr.R(ft), R0, 0);
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if (doCheck) {
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SetCC(CC_AL);
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}
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break;
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default:
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Comp_Generic(op);
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return;
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}
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}
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void Jit::Comp_FPUComp(u32 op) {
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CONDITIONAL_DISABLE;
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int opc = op & 0xF;
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if (opc >= 8) opc -= 8; // alias
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if (opc == 0)//f, sf (signalling false)
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{
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MOVI2R(R0, 0);
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STR(R0, CTXREG, offsetof(MIPSState, fpcond));
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return;
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}
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int fs = _FS;
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int ft = _FT;
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fpr.MapInIn(fs, ft);
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VCMP(fpr.R(fs), fpr.R(ft));
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VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
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switch(opc)
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{
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case 1: // un, ngle (unordered)
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SetCC(CC_VS);
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MOVI2R(R0, 1);
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SetCC(CC_VC);
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break;
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case 2: // eq, seq (equal, ordered)
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SetCC(CC_EQ);
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MOVI2R(R0, 1);
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SetCC(CC_NEQ);
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break;
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case 3: // ueq, ngl (equal, unordered)
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SetCC(CC_EQ);
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MOVI2R(R0, 1);
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SetCC(CC_NEQ);
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MOVI2R(R0, 0);
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SetCC(CC_VS);
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MOVI2R(R0, 1);
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SetCC(CC_AL);
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STR(R0, CTXREG, offsetof(MIPSState, fpcond));
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return;
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case 4: // olt, lt (less than, ordered)
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SetCC(CC_LO);
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MOVI2R(R0, 1);
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SetCC(CC_HS);
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break;
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case 5: // ult, nge (less than, unordered)
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SetCC(CC_LT);
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MOVI2R(R0, 1);
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SetCC(CC_GE);
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break;
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case 6: // ole, le (less equal, ordered)
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SetCC(CC_LS);
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MOVI2R(R0, 1);
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SetCC(CC_HI);
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break;
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case 7: // ule, ngt (less equal, unordered)
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SetCC(CC_LE);
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MOVI2R(R0, 1);
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SetCC(CC_GT);
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break;
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default:
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Comp_Generic(op);
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return;
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}
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MOVI2R(R0, 0);
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SetCC(CC_AL);
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STR(R0, CTXREG, offsetof(MIPSState, fpcond));
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}
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void Jit::Comp_FPU2op(u32 op)
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{
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CONDITIONAL_DISABLE;
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int fs = _FS;
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int fd = _FD;
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// logBlocks = 1;
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switch (op & 0x3f)
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{
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case 4: //F(fd) = sqrtf(F(fs)); break; //sqrt
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fpr.MapDirtyIn(fd, fs);
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VSQRT(fpr.R(fd), fpr.R(fs));
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break;
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case 5: //F(fd) = fabsf(F(fs)); break; //abs
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fpr.MapDirtyIn(fd, fs);
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VABS(fpr.R(fd), fpr.R(fs));
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break;
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case 6: //F(fd) = F(fs); break; //mov
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fpr.MapDirtyIn(fd, fs);
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VMOV(fpr.R(fd), fpr.R(fs));
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break;
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case 7: //F(fd) = -F(fs); break; //neg
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fpr.MapDirtyIn(fd, fs);
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VNEG(fpr.R(fd), fpr.R(fs));
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break;
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case 12: //FsI(fd) = (int)floorf(F(fs)+0.5f); break; //round.w.s
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fpr.MapDirtyIn(fd, fs);
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VCVT(fpr.R(fd), fpr.R(fs), TO_INT | IS_SIGNED);
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break;
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case 13: //FsI(fd) = Rto0(F(fs))); break; //trunc.w.s
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fpr.MapDirtyIn(fd, fs);
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VCVT(fpr.R(fd), fpr.R(fs), TO_INT | IS_SIGNED | ROUND_TO_ZERO);
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break;
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case 14: //FsI(fd) = (int)ceilf (F(fs)); break; //ceil.w.s
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fpr.MapDirtyIn(fd, fs);
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MOVI2F(S0, 0.5f, R0);
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VADD(S0,fpr.R(fs),S0);
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VCVT(fpr.R(fd), S0, TO_INT | IS_SIGNED);
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break;
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case 15: //FsI(fd) = (int)floorf(F(fs)); break; //floor.w.s
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fpr.MapDirtyIn(fd, fs);
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MOVI2F(S0, 0.5f, R0);
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VSUB(S0,fpr.R(fs),S0);
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VCVT(fpr.R(fd), S0, TO_INT | IS_SIGNED);
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break;
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case 32: //F(fd) = (float)FsI(fs); break; //cvt.s.w
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fpr.MapDirtyIn(fd, fs);
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VCVT(fpr.R(fd), fpr.R(fs), TO_FLOAT | IS_SIGNED);
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break;
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case 36: //FsI(fd) = (int) F(fs); break; //cvt.w.s
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fpr.MapDirtyIn(fd, fs);
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LDR(R0, CTXREG, offsetof(MIPSState, fcr31));
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AND(R0, R0, Operand2(3));
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// MIPS Rounding Mode:
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// 0: Round nearest
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// 1: Round to zero
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// 2: Round up (ceil)
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// 3: Round down (floor)
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CMP(R0, Operand2(2));
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SetCC(CC_GE); MOVI2F(S0, 0.5f, R1);
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SetCC(CC_GT); VSUB(S0,fpr.R(fs),S0);
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SetCC(CC_EQ); VADD(S0,fpr.R(fs),S0);
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SetCC(CC_GE); VCVT(fpr.R(fd), S0, TO_INT | IS_SIGNED); /* 2,3 */
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SetCC(CC_AL);
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CMP(R0, Operand2(1));
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SetCC(CC_EQ); VCVT(fpr.R(fd), fpr.R(fs), TO_INT | IS_SIGNED | ROUND_TO_ZERO); /* 1 */
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SetCC(CC_LT); VCVT(fpr.R(fd), fpr.R(fs), TO_INT | IS_SIGNED); /* 0 */
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SetCC(CC_AL);
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break;
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default:
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DISABLE;
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}
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}
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void Jit::Comp_mxc1(u32 op)
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{
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CONDITIONAL_DISABLE;
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int fs = _FS;
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int rt = _RT;
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switch((op >> 21) & 0x1f)
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{
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case 0: // R(rt) = FI(fs); break; //mfc1
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// Let's just go through RAM for now.
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fpr.FlushR(fs);
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gpr.MapReg(rt, MAP_DIRTY | MAP_NOINIT);
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LDR(gpr.R(rt), CTXREG, fpr.GetMipsRegOffset(fs));
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return;
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case 2: //cfc1
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if (fs == 31)
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{
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gpr.MapReg(rt, MAP_DIRTY | MAP_NOINIT);
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LDR(R0, CTXREG, offsetof(MIPSState, fpcond));
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AND(R0, R0, Operand2(1)); // Just in case
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LDR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
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BIC(gpr.R(rt), gpr.R(rt), Operand2(0x1 << 23));
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ORR(gpr.R(rt), gpr.R(rt), Operand2(R0, ST_LSL, 23));
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}
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else if (fs == 0)
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{
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gpr.MapReg(rt, MAP_DIRTY | MAP_NOINIT);
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LDR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr0));
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}
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return;
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case 4: //FI(fs) = R(rt); break; //mtc1
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// Let's just go through RAM for now.
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gpr.FlushR(rt);
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fpr.MapReg(fs, MAP_DIRTY | MAP_NOINIT);
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VLDR(fpr.R(fs), CTXREG, gpr.GetMipsRegOffset(rt));
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return;
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case 6: //ctc1
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if (fs == 31)
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{
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gpr.MapReg(rt, 0);
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// Hardware rounding method.
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// Left here in case it is faster than conditional method.
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/*
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AND(R0, gpr.R(rt), Operand2(3));
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// MIPS Rounding Mode <-> ARM Rounding Mode
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// 0, 1, 2, 3 <-> 0, 3, 1, 2
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CMP(R0, Operand2(1));
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SetCC(CC_EQ); ADD(R0, R0, Operand2(2));
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SetCC(CC_GT); SUB(R0, R0, Operand2(1));
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SetCC(CC_AL);
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// Load and Store RM to FPSCR
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VMRS(R1);
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BIC(R1, R1, Operand2(0x3 << 22));
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ORR(R1, R1, Operand2(R0, ST_LSL, 22));
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VMSR(R1);
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*/
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// Update MIPS state
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STR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
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MOV(R0, Operand2(gpr.R(rt), ST_LSR, 23));
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AND(R0, R0, Operand2(1));
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STR(R0, CTXREG, offsetof(MIPSState, fpcond));
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}
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return;
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}
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}
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} // namespace MIPSComp
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