ppsspp/Core/MIPS/MIPSVFPUUtils.h

// Copyright (c) 2012- PPSSPP Project.

// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, version 2.0 or later versions.

// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License 2.0 for more details.

// A copy of the GPL 2.0 should have been included with the program.
// If not, see http://www.gnu.org/licenses/

// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.

#pragma once

#include <array>
#include <cmath>
#include <string>
#include "Common/CommonTypes.h"
#include "Core/MIPS/MIPS.h"

#define _VD (op & 0x7F)
#define _VS ((op>>8) & 0x7F)
#define _VT ((op>>16) & 0x7F)

inline int Xpose(int v) {
	return v^0x20;
}

// Half of PI, or 90 degrees.
#ifndef M_PI_2
#define M_PI_2     1.57079632679489661923
#endif

// The VFPU uses weird angles where 4.0 represents a full circle. This makes it possible to return
// exact 1.0/-1.0 values at certain angles.
//
// The current code attempts to match VFPU sin/cos exactly.
// Possibly affected games:
//     Final Fantasy III               (#2921 )
//     Hitman Reborn 2                 (#12900)
//     Cho Aniki Zero                  (#13705)
//     Hajime no Ippo                  (#13671) 
//     Dissidia Duodecim Final Fantasy (#6710 )
//
// Messing around with the modulo functions? try https://www.desmos.com/calculator.

extern float vfpu_sin(float);
extern float vfpu_cos(float);
extern void vfpu_sincos(float, float&, float&);
// vfpu_sincos with the sine in the low 32 bits of the result and the cosine in the high, for the JITs.
extern double vfpu_sincos_packed(float);

extern float vfpu_asin(float);

// vmin and vmax order values by this key: zeros and denormals are all equal (0), and otherwise
// -NaN < -inf < negative < positive < inf < NaN, larger mantissas farther from zero. A tie returns
// the second operand, and the result keeps its bits (cpu/vfpu/minmax_zero, minmax_tie).
inline int32_t vfpu_minmax_key(uint32_t x) {
	if ((x & 0x7F800000) == 0)
		return 0;
	return (int32_t)(x ^ ((uint32_t)((int32_t)x >> 31) >> 1));
}

inline float vfpu_clamp(float v, float min, float max) {
	// Note: NAN is preserved, and -0.0 becomes +0.0 if min=+0.0.
	return v >= max ? max : (v <= min ? min : v);
}

float vfpu_dot(const float a[4], const float b[4]);
// The portable version vfpu_dot is checked against.
float vfpu_dot_reference(const float a[4], const float b[4]);
// vfpu_dot on hosts with no SIMD version.
float vfpu_dot_scalar(const float a[4], const float b[4]);
// Four vfpu_dot()s against v, over the first terms lanes: out[k] uses block[4 * i + k] for lane i,
// or block[4 * k + i] if transposed (see IROp::Vec4VfpuMultiDot).
void vfpu_multi_dot(float out[4], const float block[16], const float v[4], int terms, bool transposed);
float vfpu_sqrt(float a);
float vfpu_rsqrt(float a);

// vfpu_rcp, vfpu_rsqrt and vfpu_sqrt have a fast path. A segment and a
// 16-bit x2 come from w, which is the input's bits for rcp and (bits + 0x00800000) >> 1 for the
// square roots:
//   rcp    (k - (bits & 0xFF800000) + linear + square) & ~3
//   rsqrt  (k - (w & 0x7F800000) + linear + square) & ~3
//   sqrt   (k + (w & 0x7F800000) + linear + square) & ~3
// with linear = (m * x2) >> 17 (a 64-bit product), square = (n * ((t * t + 255) >> 8)) >> 9 and
// t = |(x2 >> 6) - 512|. The results are float bits, and the shifts are arithmetic.
struct VFPUFastSegment {
	uint32_t k;  // c0 plus the exponent bits of the result
	int32_t m;
	int32_t n;
	int32_t pad;  // makes the stride 16 bytes
};
extern const std::array<VFPUFastSegment, 128> vfpu_rcp_fast;
extern const std::array<VFPUFastSegment, 128> vfpu_rsqrt_fast;
extern const std::array<VFPUFastSegment, 128> vfpu_sqrt_fast;

// |x| in [2^-126, 2^126].
inline bool vfpu_rcp_is_fast(uint32_t bits) {
	return (bits << 1) - 0x01000000u <= 0xFC000000u;
}

// Positive, normal and finite, for both square roots.
inline bool vfpu_sqrt_is_fast(uint32_t bits) {
	return bits - 0x00800000u < 0x7F000000u;
}

extern float vfpu_exp2(float);
extern float vfpu_rexp2(float);
extern float vfpu_log2(float);
extern float vfpu_rcp(float);

extern void vrnd_init_default(uint32_t *rcx);
extern void vrnd_init(uint32_t seed, uint32_t *rcx);
extern uint32_t vrnd_generate(uint32_t *rcx);

inline uint32_t get_uexp(uint32_t x) {
	return (x >> 23) & 0xFF;
}

inline int32_t get_exp(uint32_t x) {
	return get_uexp(x) - 127;
}

inline int32_t get_mant(uint32_t x) {
	// Note: this returns the hidden 1.
	return (x & 0x007FFFFF) | 0x00800000;
}

inline int32_t get_sign(uint32_t x) {
	return x & 0x80000000;
}

#define VFPU_FLOAT16_EXP_MAX    0x1f
#define VFPU_SH_FLOAT16_SIGN    15
#define VFPU_MASK_FLOAT16_SIGN  0x1
#define VFPU_SH_FLOAT16_EXP     10
#define VFPU_MASK_FLOAT16_EXP   0x1f
#define VFPU_SH_FLOAT16_FRAC    0
#define VFPU_MASK_FLOAT16_FRAC  0x3ff

enum VectorSize {
	V_Single = 1,
	V_Pair = 2,
	V_Triple = 3,
	V_Quad = 4,
	V_Invalid = -1,
};

enum MatrixSize {
	M_1x1 = 1,
	M_2x2 = 2,
	M_3x3 = 3,
	M_4x4 = 4,
	M_Invalid = -1
};

inline u32 VFPU_SWIZZLE(int x, int y, int z, int w) {
	return (x << 0) | (y << 2) | (z << 4) | (w << 6);
}

inline u32 VFPU_MASK(int x, int y, int z, int w) {
	return (x << 0) | (y << 1) | (z << 2) | (w << 3);
}

inline u32 VFPU_ANY_SWIZZLE() {
	return 0x000000FF;
}

inline u32 VFPU_ABS(int x, int y, int z, int w) {
	return VFPU_MASK(x, y, z, w) << 8;
}

inline u32 VFPU_CONST(int x, int y, int z, int w) {
	return VFPU_MASK(x, y, z, w) << 12;
}

inline u32 VFPU_NEGATE(int x, int y, int z, int w) {
	return VFPU_MASK(x, y, z, w) << 16;
}

enum class VFPUConst {
	NONE = -1,
	ZERO,
	ONE,
	TWO,
	HALF,
	THREE,
	THIRD,
	FOURTH,
	SIXTH,
};

inline u32 VFPU_MAKE_CONSTANTS(VFPUConst x, VFPUConst y, VFPUConst z, VFPUConst w) {
	u32 result = 0;
	if (x != VFPUConst::NONE) {
		// This sets the constant flag and the swizzle/abs flags for the right constant.
		result |= (((int)x & 3) << 0) | (((int)x & 4) << 6) | (1 << 12);
	}
	if (y != VFPUConst::NONE) {
		result |= (((int)y & 3) << 2) | (((int)y & 4) << 7) | (1 << 13);
	}
	if (z != VFPUConst::NONE) {
		result |= (((int)z & 3) << 4) | (((int)z & 4) << 8) | (1 << 14);
	}
	if (w != VFPUConst::NONE) {
		result |= (((int)w & 3) << 6) | (((int)w & 4) << 9) | (1 << 15);
	}
	return result;
}

u32 VFPURewritePrefix(MIPSState *mips, int ctrl, u32 remove, u32 add);

void ReadMatrix(const MIPSState *mips, float *rd, MatrixSize size, int reg);
void WriteMatrix(MIPSState *mips,const float *rs, MatrixSize size, int reg);

void ReadVector(const MIPSState *mips, float *rd, VectorSize N, int reg);
void WriteVector(MIPSState *mips, const float *rs, VectorSize N, int reg);

void GetVectorRegs(u8 regs[4], VectorSize N, int vectorReg);
void GetMatrixRegs(u8 regs[16], MatrixSize N, int matrixReg);
// True if the matrix's row or column offset makes it wrap around the end of the 4x4 block (like a
// 4x4 E623), which GetMatrixRegs handles but code that assumes whole columns doesn't.
bool MatrixWrapsAround(int matrixReg, MatrixSize N);
 
// Translate between vector and matrix size. Possibly we should simply
// join the two enums, but the type safety is kind of nice.
VectorSize GetVectorSize(MatrixSize sz);
MatrixSize GetMatrixSize(VectorSize sz);

// Note that if matrix is a transposed matrix (E format), GetColumn will actually return rows,
// and vice versa.
int GetColumnName(int matrix, MatrixSize msize, int column, int offset);
int GetRowName(int matrix, MatrixSize msize, int row, int offset);

int GetMatrixName(int matrix, MatrixSize msize, int column, int row, bool transposed);

void GetMatrixColumns(int matrixReg, MatrixSize msize, u8 vecs[4]);
void GetMatrixRows(int matrixReg, MatrixSize msize, u8 vecs[4]);

enum MatrixOverlapType {
	OVERLAP_NONE = 0,
	OVERLAP_PARTIAL = 1,
	OVERLAP_EQUAL = 2,
	// Transposed too?  (same space but transposed)
};

MatrixOverlapType GetMatrixOverlap(int m1, int m2, MatrixSize msize);

// Returns a number from 0-7, good for checking overlap for 4x4 matrices.
static inline int GetMtx(int matrixReg) {
	return (matrixReg >> 2) & 7;
}

static inline VectorSize GetVecSize(MIPSOpcode op) {
	int a = (op >> 7) & 1;
	int b = (op >> 14) & 2;
	return (VectorSize)(a + b + 1);  // Safe, there are no other possibilities
}

static inline MatrixSize GetMtxSize(MIPSOpcode op) {
	int a = (op >> 7) & 1;
	int b = (op >> 14) & 2;
	return (MatrixSize)(a + b + 1);  // Safe, there are no other possibilities
}

VectorSize GetQuarterVectorSizeSafe(VectorSize sz);
VectorSize GetQuarterVectorSize(VectorSize sz);
VectorSize GetHalfVectorSizeSafe(VectorSize sz);
VectorSize GetHalfVectorSize(VectorSize sz);
VectorSize GetQuadrupleVectorSizeSafe(VectorSize sz);
VectorSize GetQuadrupleVectorSize(VectorSize sz);
VectorSize GetDoubleVectorSizeSafe(VectorSize sz);
VectorSize GetDoubleVectorSize(VectorSize sz);
VectorSize MatrixVectorSizeSafe(MatrixSize sz);
VectorSize MatrixVectorSize(MatrixSize sz);

static inline int GetNumVectorElements(VectorSize sz) {
	switch (sz) {
	case V_Single: return 1;
	case V_Pair:   return 2;
	case V_Triple: return 3;
	case V_Quad:   return 4;
	default:       return 1;   // let's not confuse static analyzers more than necessary. Anyway, in reality this is unreachable.
	}
}

int GetMatrixSideSafe(MatrixSize sz);
int GetMatrixSide(MatrixSize sz);
std::string GetVectorNotation(int reg, VectorSize size);
std::string GetMatrixNotation(int reg, MatrixSize size);
static inline bool IsMatrixTransposed(int matrixReg) {
	return (matrixReg >> 5) & 1;
}
static inline bool IsVectorColumn(int vectorReg) {
	return !((vectorReg >> 5) & 1);
}
static inline int TransposeMatrixReg(int matrixReg) {
	return matrixReg ^ 0x20;
}
int GetVectorOverlap(int reg1, VectorSize size1, int reg2, VectorSize size2);

bool GetVFPUCtrlMask(int reg, u32 *mask);
// Bits a write to the register always sets, on top of the mask: the RNG state registers keep
// 0x3F800000 in their top bits whatever is written (cpu/vfpu/vrnd).
u32 GetVFPUCtrlSetBits(int reg);

float Float16ToFloat32(unsigned short l);

// vh2f and vf2h, bit-exact to the hardware (cpu/vfpu/specials). vf2h truncates the mantissa,
// flushes below 2^-14 to zero and keeps the low ten mantissa bits of a NaN; vh2f flushes
// subnormal halves and keeps inf/NaN mantissa bits unshifted.
u32 vfpu_h2f(u16 h);
// The same, as a float (vfim).
float vfpu_h2f_float(u16 h);

// How the debuggers show a VFPU register. The multi-part modes list the lowest part first.
enum class VFPUDisplayMode {
	Float,
	HalfFloat,
	Hex,
	Bytes,
	Shorts,
	Ints,
	COUNT,
};
extern const char *const g_vfpuDisplayModeNames[(int)VFPUDisplayMode::COUNT];
void FormatVFPUValue(char *out, size_t outSize, u32 value, VFPUDisplayMode mode);
// vh2f of the lower or upper half of a word, with the word and result as float bits. For the JITs.
float vfpu_h2f_lower(float word);
float vfpu_h2f_upper(float word);
u16 vfpu_f2h(u32 f);