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Henrik RydgårdandClaude Opus 5.5
533baffb24
A new IR op, Vec4VfpuMultiDot, does four vfpu_dot()s against one vector, the other operands being the rows or Vec4s of a 4x4 block of registers. The frontend emits it for vmmul and vtfm/vhtfm, and for runs of vdot that fit it, like a matrix times a vector written out. On ARM64 it calls a routine that has the dots in lanes rather than the terms, so nothing is horizontal and nothing goes through the integer registers. The block comes in with LD1, or LD4 for the transposed form, when none of it is in host registers. The IR interpreter runs it through vfpu_dot(); the other backends don't get it yet. The CPU fuzzer gets runs of vdot shaped for it, and finds no difference between the cores on them. There's a routine per number of terms, so vdot.t runs don't pay for a fourth. The vector's significands are worked out once and multiplied by element, and the rounding at the end is UCVTF's in round-to-nearest, which is what games run in; the integer version stays for the other modes. The routine saves nothing, and the call site keeps only those registers it clobbers that hold guest state. JitDotBench, ns per dot: vtfm4.q 3.40, vmmul.q 3.12, a run of vdot.t 2.83, against 4.6 for single dots. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
73 lines
2.0 KiB
C
73 lines
2.0 KiB
C
// Copyright (c) 2016- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include "Core/MIPS/IR/IRInst.h"
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struct IRInstMeta {
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union {
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IRInst i;
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struct {
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IROp op;
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union {
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IRReg dest;
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IRReg src3;
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};
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IRReg src1;
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IRReg src2;
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u32 constant;
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};
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};
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IRMeta m;
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};
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static_assert(offsetof(IRInst, src2) == offsetof(IRInstMeta, src2));
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inline IRInstMeta GetIRMeta(const IRInst &inst) {
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return { { inst }, *GetIRMeta(inst.op) };
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}
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bool IRReadsFromFPR(const IRInstMeta &inst, int reg, bool *directly = nullptr);
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bool IRReadsFromGPR(const IRInstMeta &inst, int reg, bool *directly = nullptr);
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bool IRWritesToGPR(const IRInstMeta &inst, int reg);
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bool IRWritesToFPR(const IRInstMeta &inst, int reg);
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int IRDestGPR(const IRInstMeta &inst);
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int IRDestFPRs(const IRInstMeta &inst, IRReg regs[4]);
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int IRReadsFromGPRs(const IRInstMeta &inst, IRReg regs[4]);
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// A block (M) and a Vec4.
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enum { IR_MAX_FPR_READS = 20 };
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int IRReadsFromFPRs(const IRInstMeta &inst, IRReg regs[IR_MAX_FPR_READS]);
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struct IRSituation {
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int lookaheadCount;
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int currentIndex;
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const IRInst *instructions;
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int numInstructions;
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};
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enum class IRUsage {
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UNKNOWN,
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UNUSED,
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READ,
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WRITE,
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CLOBBERED,
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};
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IRUsage IRNextGPRUsage(int gpr, const IRSituation &info);
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IRUsage IRNextFPRUsage(int fpr, const IRSituation &info);
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