Henrik RydgårdandClaude Opus 5.5 f8004442c8 RISC-V IR: Allocate the saved registers before the temporaries ...

After the registers usable by compressed instructions, prefer s2-s7 and
fs2-fs11, so that fewer values have to be flushed around calls. The
dispatcher already saves them.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>

2026-09-24 16:22:41 -06:00

..

ARM

VFPU: Fix vrot with the angle in a destination lane

2026-09-24 16:22:41 -06:00

ARM64

IR: Compute vrot's sine and cosine in one call

2026-09-24 16:22:41 -06:00

fake

Prep for plumbing the MIPS context pointer into the interpreter.

2026-08-12 11:25:06 +02:00

IR

IR: Compute vrot's sine and cosine in one call

2026-09-24 16:22:41 -06:00

JitCommon

Add a MIPSState context pointer to the JitAt call

2026-09-21 17:34:10 -06:00

LoongArch64

RISC-V/LoongArch IR: Get vrot's sine and cosine from one call

2026-09-24 16:22:41 -06:00

RiscV

RISC-V IR: Allocate the saved registers before the temporaries

2026-09-24 16:22:41 -06:00

x86

IR: Compute vrot's sine and cosine in one call

2026-09-24 16:22:41 -06:00

Interpreter.cpp

FPU: sqrt.s of a negative gives the PSP's positive NaN

2026-09-22 14:25:41 -06:00

Interpreter.h

Make instruction cache invalidation (for us, jit cache invalidation) clearer

2026-08-16 16:59:52 +02:00

InterpreterDispatch.cpp

Add dummy interpreter implementations for the basic COP0 instructions

2026-08-13 11:34:00 +02:00

InterpreterDispatch.h

Plumb an explicit MIPSState *mips through the interpreter's Int_* handlers

2026-08-12 14:02:19 +02:00

InterpreterVFPU.cpp

VFPU: vsqrt, vrsq, vrcp and vnrcp are exact in every backend

2026-09-24 12:24:42 -06:00

InterpreterVFPU.h

Plumb an explicit MIPSState *mips through the interpreter's Int_* handlers

2026-08-12 14:02:19 +02:00

MIPS.cpp

Honor the guest FPU rounding mode outside x86 and arm64

2026-09-21 15:36:49 -06:00

MIPS.h

Interpreter: implement the FPU divide-by-zero exception

2026-08-29 23:40:48 +02:00

MIPSAnalyst.cpp

Interpreter: assorted fixes found while reviewing Core/MIPS

2026-09-19 10:02:46 -06:00

MIPSAnalyst.h

Interpreter: assorted fixes found while reviewing Core/MIPS

2026-09-19 10:02:46 -06:00

MIPSAsm.cpp

Make instruction cache invalidation (for us, jit cache invalidation) clearer

2026-08-16 16:59:52 +02:00

MIPSAsm.h

Fix the API for MIPSAssembleOpcode to remove a global

2025-11-03 16:08:07 +01:00

MIPSCodeUtils.cpp

Warning fixes, alignment checks

2025-05-15 09:48:23 +02:00

MIPSCodeUtils.h

Move the dump playback mips code to Playback.cpp. Assorted cleanup.

2024-12-10 01:27:25 +01:00

MIPSDebugInterface.cpp

ImDebugger: add "Run to here, next frame", gated on the flip count

2026-08-18 10:59:08 +02:00

MIPSDebugInterface.h

Win32 debugger: stop cutting off register values in CtrlRegisterList

2026-09-12 13:46:12 -06:00

MIPSDis.cpp

Fix some function name shenanigans

2026-08-14 14:55:06 +02:00

MIPSDis.h

Core: Cleanup disasm buffer usage.

2023-04-29 09:07:25 -07:00

MIPSDisVFPU.cpp

Fix assembly/disassembly for various VFPU opcodes

2026-08-11 10:10:56 -04:00

MIPSDisVFPU.h

Improve debugger assemble/disassemble compatiblity

2026-07-07 20:30:51 -04:00

MIPSStackWalk.cpp

More memory cleanup

2026-08-11 20:12:10 +02:00

MIPSStackWalk.h

…

MIPSTables.cpp

Interpreter: assorted fixes found while reviewing Core/MIPS

2026-09-19 10:02:46 -06:00

MIPSTables.h

Plumb an explicit MIPSState *mips through the interpreter's Int_* handlers

2026-08-12 14:02:19 +02:00

MIPSTracer.cpp

MIPSTracer: don't index trace_info with stale block indices

2026-09-19 10:02:54 -06:00

MIPSTracer.h

MIPSTracer: don't index trace_info with stale block indices

2026-09-19 10:02:54 -06:00

MIPSVFPUUtils.cpp

IR: Compute vrot's sine and cosine in one call

2026-09-24 16:22:41 -06:00

MIPSVFPUUtils.h

IR: Compute vrot's sine and cosine in one call

2026-09-24 16:22:41 -06:00