Unknown W. Brackets a450a79f52 jit-ir: Optimize loads to transfers if possible. ...

These (especially float <-> gpr) happen in all games, but gpr->gpr is
especially common in some minis.  Good to reduce bloat.

2016-05-29 18:34:41 -07:00

..

IRAsm.cpp

Initial commit for IRJit

2016-05-07 13:58:29 +02:00

IRCompALU.cpp

jit-ir: Add div/divu instructions.

2016-05-14 19:23:52 -07:00

IRCompBranch.cpp

Symbian buildfix, fix for fpu test

2016-05-14 15:26:43 +02:00

IRCompFPU.cpp

IR: More VFPU. Support normal fp compares.

2016-05-12 20:16:15 +02:00

IRCompLoadStore.cpp

Minor build and other fixes

2016-05-13 19:31:27 +02:00

IRCompVFPU.cpp

jit-ir: Mark prefixes unknown in mtv.

2016-05-17 21:22:57 -07:00

IRFrontend.cpp

jit-ir: Add load/store reorder and merge passes.

2016-05-17 21:24:13 -07:00

IRFrontend.h

Add some missing override definitions.

2016-05-21 09:29:03 -07:00

IRInst.cpp

Fix bug in vus2i (thanks unknown), recognize vectors in IR disasm

2016-05-15 23:35:33 +02:00

IRInst.h

Most of vi2x

2016-05-15 11:46:01 +02:00

IRInterpreter.cpp

Fix bug in vus2i (thanks unknown), recognize vectors in IR disasm

2016-05-15 23:35:33 +02:00

IRInterpreter.h

jit-ir: Implement bit reverse instruction.

2016-05-14 18:21:42 -07:00

IRJit.cpp

Fix timing drift on CoreTiming::ForceCheck().

2016-05-15 12:43:34 -07:00

IRJit.h

Add some missing override definitions.

2016-05-21 09:29:03 -07:00

IRPassSimplify.cpp

jit-ir: Optimize loads to transfers if possible.

2016-05-29 18:34:41 -07:00

IRPassSimplify.h

jit-ir: Add load/store reorder and merge passes.

2016-05-17 21:24:13 -07:00

IRRegCache.cpp

jit-ir: Less instructions cause flushing in constant propagation.

2016-05-08 23:25:08 +02:00

IRRegCache.h

jit-ir: Less instructions cause flushing in constant propagation.

2016-05-08 23:25:08 +02:00