Unknown W. Brackets 5749ae09d0 interp: Correct vmfvc register behavior. ...

The target and source registers were completely wrong.

2019-03-31 13:41:48 -07:00

..

Asm.cpp

jit: Remove unused breakpoint code.

2018-06-06 17:31:56 -07:00

CompALU.cpp

Jit: Respect flags for jit types and features.

2019-02-03 14:57:08 -08:00

CompBranch.cpp

Reduce a ERROR_LOG_REPORT to a warning (vfpu branches in delay slots)

2017-11-11 19:39:44 +01:00

CompFPU.cpp

Jit: Respect flags for jit types and features.

2019-02-03 14:57:08 -08:00

CompLoadStore.cpp

Jit: Respect flags for jit types and features.

2019-02-03 14:57:08 -08:00

CompReplace.cpp

Get rid of ugly alignment macros and some other cruft, we now have alignas(16) from C++11

2017-08-31 01:14:51 +02:00

CompVFPU.cpp

interp: Correct vmfvc register behavior.

2019-03-31 13:41:48 -07:00

IRToX86.cpp

cmake: Detect features at compile time

2016-10-19 12:31:19 +02:00

IRToX86.h

Add missing cases to simplify pass

2016-05-15 23:39:42 +02:00

Jit.cpp

jit: Apply hasSetRounding at compile time.

2018-04-01 10:36:16 -07:00

Jit.h

jit: Remove unused breakpoint code.

2018-06-06 17:31:56 -07:00

JitSafeMem.cpp

Debugger: Add memory breakpoint management.

2018-06-08 06:59:18 -07:00

JitSafeMem.h

SafeMem: Remove the "far" optimization that saves 3 bytes sometimes but is really dangerous and not worth the complexity.

2017-08-30 09:58:30 +02:00

RegCache.cpp

X64/X86: Even more use of the context register

2017-07-05 13:21:35 +02:00

RegCache.h

Fix various minor warnings.

2016-03-20 14:17:51 -07:00

RegCacheFPU.cpp

More RIP fixes

2017-07-07 15:46:14 +02:00

RegCacheFPU.h

x64: Enable non-RIP addressing for FPU registers

2017-07-07 11:33:07 +02:00