Unknown W. Brackets b11858d9a0 irjit: Properly account for delay slots in size. ...

Otherwise we think blocks are 4 bytes too short, which can affect
invalidation.

2018-01-01 22:54:40 -08:00

..

IRAsm.cpp

Initial commit for IRJit

2016-05-07 13:58:29 +02:00

IRCompALU.cpp

irjit: Cleanup some invalid op handling.

2018-01-01 08:38:11 -08:00

IRCompBranch.cpp

irjit: Properly account for delay slots in size.

2018-01-01 22:54:40 -08:00

IRCompFPU.cpp

irjit: Cleanup some invalid op handling.

2018-01-01 08:38:11 -08:00

IRCompLoadStore.cpp

irjit: Implement lwl/lwr/swl/swr.

2018-01-01 08:38:13 -08:00

IRCompVFPU.cpp

irjit: Cleanup some invalid op handling.

2018-01-01 08:38:11 -08:00

IRFrontend.cpp

irjit: Properly account for delay slots in size.

2018-01-01 22:54:40 -08:00

IRFrontend.h

irjit: Add options for compile/optimize steps.

2018-01-01 08:38:12 -08:00

IRInst.cpp

irjit: Add extra temps to make lwl/swl/etc. easier.

2018-01-01 08:38:11 -08:00

IRInst.h

irjit: Add options for compile/optimize steps.

2018-01-01 08:38:12 -08:00

IRInterpreter.cpp

irjit: Allow continuing from mips break.

2017-12-25 10:21:22 -08:00

IRInterpreter.h

jit-ir: Implement bit reverse instruction.

2016-05-14 18:21:42 -07:00

IRJit.cpp

irjit: Add options for compile/optimize steps.

2018-01-01 08:38:12 -08:00

IRJit.h

irjit: Speed up icache block invalidation.

2017-12-31 10:37:09 -08:00

IRPassSimplify.cpp

irjit: Add options for compile/optimize steps.

2018-01-01 08:38:12 -08:00

IRPassSimplify.h

irjit: Add options for compile/optimize steps.

2018-01-01 08:38:12 -08:00

IRRegCache.cpp

jit-ir: Less instructions cause flushing in constant propagation.

2016-05-08 23:25:08 +02:00

IRRegCache.h

jit-ir: Less instructions cause flushing in constant propagation.

2016-05-08 23:25:08 +02:00