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Henrik RydgårdandClaude Opus 5.5
b7b4a265b7
The interpreter's MMIO dispatch was a hardcoded chain for GPIO and the syscon serial port. Devices now register an address range in Core/HW/MMIO and get each access with its width and the MIPSState making it, for registers that answer each CPU differently. An access no device handles is logged and reads as poison, as before. GPIO and syscon serial become the first two devices. They're reset at boot, which they never were, and saved in savestates (SaveStart section version 4). ll/sc, lwl/lwr and lwc1/swc1 reach MMIO in the interpreter too, and kernel blocks leave lwc1/swc1 to it like the other loads and stores. swl/swr and lv/sv still treat it as a bad address. TestMMIO runs a kernel-mode access on each core and the registers through a savestate. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>