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https://github.com/hrydgard/ppsspp.git
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103 lines
4.3 KiB
C++
103 lines
4.3 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include "Common/LoongArch64Emitter.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/IR/IRJit.h"
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#include "Core/MIPS/IR/IRRegCache.h"
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namespace LoongArch64JitConstants {
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const LoongArch64Gen::LoongArch64Reg DOWNCOUNTREG = LoongArch64Gen::R28;
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const LoongArch64Gen::LoongArch64Reg JITBASEREG = LoongArch64Gen::R29;
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const LoongArch64Gen::LoongArch64Reg CTXREG = LoongArch64Gen::R30;
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const LoongArch64Gen::LoongArch64Reg MEMBASEREG = LoongArch64Gen::R31;
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const LoongArch64Gen::LoongArch64Reg SCRATCH1 = LoongArch64Gen::R12;
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const LoongArch64Gen::LoongArch64Reg SCRATCH2 = LoongArch64Gen::R13;
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const LoongArch64Gen::LoongArch64Reg SCRATCHF1 = LoongArch64Gen::F8;
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const LoongArch64Gen::LoongArch64Reg SCRATCHF2 = LoongArch64Gen::F9;
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} // namespace LoongArch64JitConstants
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class LoongArch64RegCache : public IRNativeRegCacheBase {
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public:
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LoongArch64RegCache(MIPSComp::JitOptions *jo);
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void Init(LoongArch64Gen::LoongArch64Emitter *emitter);
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// May fail and return INVALID_REG if it needs flushing.
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LoongArch64Gen::LoongArch64Reg TryMapTempImm(IRReg reg);
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// Returns an LA register containing the requested MIPS register.
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LoongArch64Gen::LoongArch64Reg MapGPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);
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LoongArch64Gen::LoongArch64Reg MapGPRAsPointer(IRReg reg);
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LoongArch64Gen::LoongArch64Reg MapFPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);
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LoongArch64Gen::LoongArch64Reg MapVec4(IRReg first, MIPSMap mapFlags = MIPSMap::INIT);
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LoongArch64Gen::LoongArch64Reg MapWithFPRTemp(const IRInst &inst);
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bool IsNormalized32(IRReg reg);
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// Copies to another reg if specified, otherwise same reg.
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LoongArch64Gen::LoongArch64Reg Normalize32(IRReg reg, LoongArch64Gen::LoongArch64Reg destReg = LoongArch64Gen::INVALID_REG);
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void FlushBeforeCall();
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LoongArch64Gen::LoongArch64Reg GetAndLockTempGPR();
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LoongArch64Gen::LoongArch64Reg R(IRReg preg); // Returns a cached register, while checking that it's NOT mapped as a pointer
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LoongArch64Gen::LoongArch64Reg RPtr(IRReg preg); // Returns a cached register, if it has been mapped as a pointer
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LoongArch64Gen::LoongArch64Reg F(IRReg preg);
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LoongArch64Gen::LoongArch64Reg V(IRReg preg);
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// These are called once on startup to generate functions, that you should then call.
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void EmitLoadStaticRegisters();
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void EmitSaveStaticRegisters();
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protected:
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void SetupInitialRegs() override;
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const StaticAllocation *GetStaticAllocations(int &count) const override;
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const int *GetAllocationOrder(MIPSLoc type, MIPSMap flags, int &count, int &base) const override;
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void AdjustNativeRegAsPtr(IRNativeReg nreg, bool state) override;
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bool IsNativeRegCompatible(IRNativeReg nreg, MIPSLoc type, MIPSMap flags, int lanes) override;
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void LoadNativeReg(IRNativeReg nreg, IRReg first, int lanes) override;
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void StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) override;
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void SetNativeRegValue(IRNativeReg nreg, uint32_t imm) override;
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void StoreRegValue(IRReg mreg, uint32_t imm) override;
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bool TransferNativeReg(IRNativeReg nreg, IRNativeReg dest, MIPSLoc type, IRReg first, int lanes, MIPSMap flags) override;
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private:
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bool TransferVecTo1(IRNativeReg nreg, IRNativeReg dest, IRReg first, int oldlanes);
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bool Transfer1ToVec(IRNativeReg nreg, IRNativeReg dest, IRReg first, int lanes);
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LoongArch64Gen::LoongArch64Reg FromNativeReg(IRNativeReg r) {
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if (r >= NUM_LAGPR)
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return (LoongArch64Gen::LoongArch64Reg)(LoongArch64Gen::V0 + (r - NUM_LAGPR));
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return (LoongArch64Gen::LoongArch64Reg)(LoongArch64Gen::R0 + r);
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}
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LoongArch64Gen::LoongArch64Emitter *emit_ = nullptr;
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enum {
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NUM_LAGPR = 32,
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NUM_LAFPR = 32,
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};
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};
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