mirror of
https://github.com/hrydgard/ppsspp.git
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Lin Runze
397 lines
10 KiB
C++
397 lines
10 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Core/MemMap.h"
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#include "Core/MIPS/LoongArch64/LoongArch64Jit.h"
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#include "Core/MIPS/LoongArch64/LoongArch64RegCache.h"
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// This file contains compilation for load/store instructions.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE. No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace LoongArch64Gen;
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using namespace LoongArch64JitConstants;
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void LoongArch64JitBackend::SetScratch1ToSrc1Address(IRReg src1) {
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regs_.MapGPR(src1);
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#ifdef MASKED_PSP_MEMORY
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SLLI_W(SCRATCH1, regs_.R(src1), 2);
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SRLI_W(SCRATCH1, SCRATCH1, 2);
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ADD_D(SCRATCH1, SCRATCH1, MEMBASEREG);
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#else
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// Clear the top bits to be safe.
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SLLI_D(SCRATCH1, regs_.R(src1), 32);
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SRLI_D(SCRATCH1, SCRATCH1, 32);
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ADD_D(SCRATCH1, SCRATCH1, MEMBASEREG);
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#endif
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}
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int32_t LoongArch64JitBackend::AdjustForAddressOffset(LoongArch64Gen::LoongArch64Reg *reg, int32_t constant, int32_t range) {
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if (constant < -2048 || constant + range > 2047) {
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#ifdef MASKED_PSP_MEMORY
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if (constant > 0)
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constant &= Memory::MEMVIEW32_MASK;
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#endif
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// It can't be this negative, must be a constant with top bit set.
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if ((constant & 0xC0000000) == 0x80000000) {
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LI(SCRATCH2, (uint32_t)constant);
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ADD_D(SCRATCH1, *reg, SCRATCH2);
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} else {
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LI(SCRATCH2, constant);
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ADD_D(SCRATCH1, *reg, SCRATCH2);
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}
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*reg = SCRATCH1;
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return 0;
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}
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return constant;
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}
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void LoongArch64JitBackend::CompIR_Load(IRInst inst) {
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CONDITIONAL_DISABLE;
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regs_.SpillLockGPR(inst.dest, inst.src1);
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LoongArch64Reg addrReg = INVALID_REG;
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if (inst.src1 == MIPS_REG_ZERO) {
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// This will get changed by AdjustForAddressOffset.
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addrReg = MEMBASEREG;
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#ifdef MASKED_PSP_MEMORY
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inst.constant &= Memory::MEMVIEW32_MASK;
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#endif
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} else if (jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) {
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addrReg = regs_.MapGPRAsPointer(inst.src1);
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} else {
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SetScratch1ToSrc1Address(inst.src1);
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addrReg = SCRATCH1;
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}
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// With NOINIT, MapReg won't subtract MEMBASEREG even if dest == src1.
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regs_.MapGPR(inst.dest, MIPSMap::NOINIT);
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regs_.MarkGPRDirty(inst.dest, true);
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s32 imm = AdjustForAddressOffset(&addrReg, inst.constant);
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// TODO: Safe memory? Or enough to have crash handler + validate?
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switch (inst.op) {
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case IROp::Load8:
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LD_BU(regs_.R(inst.dest), addrReg, imm);
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break;
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case IROp::Load8Ext:
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LD_B(regs_.R(inst.dest), addrReg, imm);
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break;
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case IROp::Load16:
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LD_HU(regs_.R(inst.dest), addrReg, imm);
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break;
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case IROp::Load16Ext:
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LD_H(regs_.R(inst.dest), addrReg, imm);
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break;
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case IROp::Load32:
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LD_W(regs_.R(inst.dest), addrReg, imm);
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break;
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case IROp::Load32Linked:
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if (inst.dest != MIPS_REG_ZERO)
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LD_W(regs_.R(inst.dest), addrReg, imm);
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regs_.SetGPRImm(IRREG_LLBIT, 1);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void LoongArch64JitBackend::CompIR_LoadShift(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Load32Left:
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case IROp::Load32Right:
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// Should not happen if the pass to split is active.
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DISABLE;
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void LoongArch64JitBackend::CompIR_FLoad(IRInst inst) {
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CONDITIONAL_DISABLE;
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LoongArch64Reg addrReg = INVALID_REG;
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if (inst.src1 == MIPS_REG_ZERO) {
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// This will get changed by AdjustForAddressOffset.
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addrReg = MEMBASEREG;
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#ifdef MASKED_PSP_MEMORY
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inst.constant &= Memory::MEMVIEW32_MASK;
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#endif
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} else if (jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) {
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addrReg = regs_.MapGPRAsPointer(inst.src1);
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} else {
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SetScratch1ToSrc1Address(inst.src1);
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addrReg = SCRATCH1;
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}
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s32 imm = AdjustForAddressOffset(&addrReg, inst.constant);
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// TODO: Safe memory? Or enough to have crash handler + validate?
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switch (inst.op) {
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case IROp::LoadFloat:
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regs_.MapFPR(inst.dest, MIPSMap::NOINIT);
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FLD_S(regs_.F(inst.dest), addrReg, imm);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void LoongArch64JitBackend::CompIR_VecLoad(IRInst inst) {
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CONDITIONAL_DISABLE;
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LoongArch64Reg addrReg = INVALID_REG;
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if (inst.src1 == MIPS_REG_ZERO) {
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// This will get changed by AdjustForAddressOffset.
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addrReg = MEMBASEREG;
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#ifdef MASKED_PSP_MEMORY
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inst.constant &= Memory::MEMVIEW32_MASK;
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#endif
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} else if (jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) {
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addrReg = regs_.MapGPRAsPointer(inst.src1);
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} else {
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SetScratch1ToSrc1Address(inst.src1);
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addrReg = SCRATCH1;
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}
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// We need to be able to address the whole 16 bytes, so offset of 12.
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s32 imm = AdjustForAddressOffset(&addrReg, inst.constant, 12);
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// TODO: Safe memory? Or enough to have crash handler + validate?
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switch (inst.op) {
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case IROp::LoadVec4:
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if (cpu_info.LOONGARCH_LSX) {
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regs_.MapVec4(inst.dest, MIPSMap::NOINIT);
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VLD(regs_.V(inst.dest), addrReg, imm);
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} else {
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for (int i = 0; i < 4; ++i) {
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// Spilling is okay.
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regs_.MapFPR(inst.dest + i, MIPSMap::NOINIT);
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FLD_S(regs_.F(inst.dest + i), addrReg, imm + 4 * i);
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}
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}
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void LoongArch64JitBackend::CompIR_Store(IRInst inst) {
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CONDITIONAL_DISABLE;
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regs_.SpillLockGPR(inst.src3, inst.src1);
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LoongArch64Reg addrReg = INVALID_REG;
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if (inst.src1 == MIPS_REG_ZERO) {
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// This will get changed by AdjustForAddressOffset.
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addrReg = MEMBASEREG;
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#ifdef MASKED_PSP_MEMORY
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inst.constant &= Memory::MEMVIEW32_MASK;
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#endif
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} else if ((jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) && inst.src3 != inst.src1) {
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addrReg = regs_.MapGPRAsPointer(inst.src1);
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} else {
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SetScratch1ToSrc1Address(inst.src1);
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addrReg = SCRATCH1;
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}
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LoongArch64Reg valueReg = regs_.TryMapTempImm(inst.src3);
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if (valueReg == INVALID_REG)
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valueReg = regs_.MapGPR(inst.src3);
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s32 imm = AdjustForAddressOffset(&addrReg, inst.constant);
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// TODO: Safe memory? Or enough to have crash handler + validate?
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switch (inst.op) {
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case IROp::Store8:
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ST_B(valueReg, addrReg, imm);
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break;
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case IROp::Store16:
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ST_H(valueReg, addrReg, imm);
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break;
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case IROp::Store32:
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ST_W(valueReg, addrReg, imm);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void LoongArch64JitBackend::CompIR_CondStore(IRInst inst) {
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CONDITIONAL_DISABLE;
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if (inst.op != IROp::Store32Conditional)
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INVALIDOP;
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regs_.SpillLockGPR(IRREG_LLBIT, inst.src3, inst.src1);
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LoongArch64Reg addrReg = INVALID_REG;
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if (inst.src1 == MIPS_REG_ZERO) {
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// This will get changed by AdjustForAddressOffset.
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addrReg = MEMBASEREG;
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#ifdef MASKED_PSP_MEMORY
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inst.constant &= Memory::MEMVIEW32_MASK;
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#endif
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} else if ((jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) && inst.src3 != inst.src1) {
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addrReg = regs_.MapGPRAsPointer(inst.src1);
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} else {
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SetScratch1ToSrc1Address(inst.src1);
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addrReg = SCRATCH1;
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}
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regs_.MapGPR(inst.src3, inst.dest == MIPS_REG_ZERO ? MIPSMap::INIT : MIPSMap::DIRTY);
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regs_.MapGPR(IRREG_LLBIT);
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s32 imm = AdjustForAddressOffset(&addrReg, inst.constant);
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// TODO: Safe memory? Or enough to have crash handler + validate?
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FixupBranch condFailed = BEQZ(regs_.R(IRREG_LLBIT));
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ST_W(regs_.R(inst.src3), addrReg, imm);
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if (inst.dest != MIPS_REG_ZERO) {
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LI(regs_.R(inst.dest), 1);
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FixupBranch finish = B();
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SetJumpTarget(condFailed);
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LI(regs_.R(inst.dest), 0);
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SetJumpTarget(finish);
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} else {
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SetJumpTarget(condFailed);
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}
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}
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void LoongArch64JitBackend::CompIR_StoreShift(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Store32Left:
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case IROp::Store32Right:
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// Should not happen if the pass to split is active.
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DISABLE;
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void LoongArch64JitBackend::CompIR_FStore(IRInst inst) {
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CONDITIONAL_DISABLE;
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LoongArch64Reg addrReg = INVALID_REG;
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if (inst.src1 == MIPS_REG_ZERO) {
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// This will get changed by AdjustForAddressOffset.
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addrReg = MEMBASEREG;
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#ifdef MASKED_PSP_MEMORY
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inst.constant &= Memory::MEMVIEW32_MASK;
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#endif
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} else if (jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) {
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addrReg = regs_.MapGPRAsPointer(inst.src1);
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} else {
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SetScratch1ToSrc1Address(inst.src1);
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addrReg = SCRATCH1;
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}
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s32 imm = AdjustForAddressOffset(&addrReg, inst.constant);
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// TODO: Safe memory? Or enough to have crash handler + validate?
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switch (inst.op) {
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case IROp::StoreFloat:
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regs_.MapFPR(inst.src3);
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FST_S(regs_.F(inst.src3), addrReg, imm);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void LoongArch64JitBackend::CompIR_VecStore(IRInst inst) {
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CONDITIONAL_DISABLE;
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LoongArch64Reg addrReg = INVALID_REG;
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if (inst.src1 == MIPS_REG_ZERO) {
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// This will get changed by AdjustForAddressOffset.
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addrReg = MEMBASEREG;
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#ifdef MASKED_PSP_MEMORY
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inst.constant &= Memory::MEMVIEW32_MASK;
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#endif
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} else if (jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) {
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addrReg = regs_.MapGPRAsPointer(inst.src1);
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} else {
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SetScratch1ToSrc1Address(inst.src1);
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addrReg = SCRATCH1;
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}
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// We need to be able to address the whole 16 bytes, so offset of 12.
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s32 imm = AdjustForAddressOffset(&addrReg, inst.constant, 12);
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// TODO: Safe memory? Or enough to have crash handler + validate?
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switch (inst.op) {
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case IROp::StoreVec4:
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if (cpu_info.LOONGARCH_LSX) {
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regs_.MapVec4(inst.src3);
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VST(regs_.V(inst.src3), addrReg, imm);
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} else {
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for (int i = 0; i < 4; ++i) {
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// Spilling is okay, though not ideal.
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regs_.MapFPR(inst.src3 + i);
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FST_S(regs_.F(inst.src3 + i), addrReg, imm + 4 * i);
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}
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}
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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} // namespace MIPSComp
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