preserve-emulation/ppsspp
1
0
Fork 0
mirror of https://github.com/hrydgard/ppsspp.git synced 2026-07-23 23:34:46 +02:00
Code Issues Packages Projects Releases Wiki Activity
33,136 Commits 78 Branches 131 Tags
fb875b94de26c9900d38f412ce96af9860a248b3
Commit Graph
70 Commits
Author SHA1 Message Date
Unknown W. Brackets 90517ace59 irjit: Validate alignment in slow memory mode. 2022-08-21 13:24:10 -07:00
Unknown W. Brackets 6715f41410 irjit: Add constructs for validing mem access. 
Basically to allow slow/fast memory to work with IR, including for
alignment checks.
 2022-08-21 13:01:23 -07:00
Unknown W. Brackets 7b081a61c8 irjit: Correct another PurgeTemps case. 
In this case:
  Mov A, B
  AndConst A, A, 1
  Load32 C, A, 0

Was still swapping the Load32 to B, not just the AndConst.

Fixes #15735.
 2022-07-27 19:38:16 -07:00
Unknown W. Brackets 5abf1362a2 irjit: Clarify PurgeTemps, guard a couple ops. 
Although I think we skip simplify passes on breakpoints entirely, safer to
exclude these ops.
 2022-07-27 19:36:53 -07:00
Unknown W. Brackets 2154f747fc irjit: Simplify more arithmetic to Movs. 
Later passes rely on things being Mov, so better to have them more often.
 2022-07-24 11:35:54 -07:00
Unknown W. Brackets 8f23025209 irjit: Add tests for IR passes. 2022-07-24 11:35:54 -07:00
Unknown W. Brackets c2a1caa2a2 irjit: Prevent corruption on purge temps pass. 
If a switch occurs and then something clobbers the dest of that switch, we
were wiping out the first of those three instructions incorrectly.
 2022-07-21 09:06:37 -07:00
Unknown W. Brackets f32f89dd90 Global: Remove some unused variables. 2021-02-15 11:59:45 -08:00
Unknown W. Brackets 5d60fa0d0d Common: Maintain C++11 support in sign extend. 2021-01-31 08:44:02 -08:00
Unknown W. Brackets 1b00da2f3a Common: Sign extend w/func not chained casts. 
Should be clearer to read and easier to get right.
 2021-01-31 01:25:52 -08:00
Unknown W. Brackets 5354459476 irjit: Update clobber flag on inst swap. 
Fixes IR in Persona 3.
 2021-01-10 16:41:45 -08:00
Unknown W. Brackets 9dcb70d502 irjit: Add disable flag for simplify passes. 2021-01-10 14:50:32 -08:00
Henrik Rydgård 4d3ec20082 ByteSwap.h results in a file name collision on some systems with byteswap.h. Fix this by merging it into BitSet.h. 2020-09-30 00:09:13 +02:00
Henrik Rydgård 40ec0d8358 Finish getting rid of basictypes.h 2020-09-29 15:51:51 +02:00
Henrik Rydgård 3162f30158 Merge base/basictypes.h into Common/Common.h (mostly). 2020-09-29 15:51:51 +02:00
Unknown W. Brackets f01e06aefd irjit: Improve multiple lwr in a row. 2018-01-07 21:06:02 -08:00
Unknown W. Brackets fbeedd333b irjit: Swap moves when it may allow clobbering. 
Example:
addiu a0, a1, a2
mov s0, a0
addiu a0, a2, a3

By swapping the mov, we can eliminate it.

Only going one back because it's common and didn't want to track reads.
 2018-01-07 21:06:02 -08:00
Unknown W. Brackets d27e428659 irjit: Convert lwr and friends to easier code. 
This makes it easier to write a (working) jit backend from IR, since these
ops are always annoying to get right.
 2018-01-07 21:06:00 -08:00
Unknown W. Brackets b11f00cead irjit: Combine lwl/lwr and swl/swr, like before. 
Still want to inline the operation, because the backend shouldn't have to
redo it every time, and we want the temps cleaned up if possible.
 2018-01-07 21:05:58 -08:00
Unknown W. Brackets c6d690e9b8 irjit: Handle Left/Right ops in passes. 2018-01-07 21:05:57 -08:00
Unknown W. Brackets cd3f4881a5 irjit: Optimize out temp lhs copies. 
Common example:
li v0, 1
beq s2, v0, somewhere
li v0, 2

Which was copying s2 before.  This pattern generally doesn't happen in
MIPS code, though, so really only catches that (very common) case.
 2018-01-07 12:11:16 -08:00
Unknown W. Brackets cffb2d61a7 irjit: Embed constant inside IRInst. 
This simplifies a bunch of code and improves compile performance by about
30%, at the cost of a bit more memory.
 2018-01-03 23:24:04 -08:00
Unknown W. Brackets b37ba9e599 irjit: Add options for compile/optimize steps. 
This way the backend can set flags for the type of IR it wants.  It's
seems too complex to combine certain things like lwl/lwr in a pass.
 2018-01-01 08:38:12 -08:00
Unknown W. Brackets 671be24105 irjit: Add extra temps to make lwl/swl/etc. easier. 2018-01-01 08:38:11 -08:00
Henrik Rydgard 5d5f10d956 Attempts to counter crashes seen in the Google Play developer console 2016-12-01 22:07:03 +01:00
Unknown W. Brackets 4578c3cb54 jit-ir: Implement memory breakpoints. 
These generally work, but likely delay slots will make downcount slightly
off, and won't resume when you hit run again without manually stepping
through them.
 2016-07-02 16:38:30 -07:00
Unknown W. Brackets a450a79f52 jit-ir: Optimize loads to transfers if possible. 
These (especially float <-> gpr) happen in all games, but gpr->gpr is
especially common in some minis.  Good to reduce bloat.
 2016-05-29 18:34:41 -07:00
Unknown W. Brackets ee31f09b67 Buildfix. 2016-05-18 07:12:21 -07:00
Unknown W. Brackets 5534fba72c jit-ir: Add load/store reorder and merge passes. 
Can do more in merge, potentially.  Maybe it's not useful...
 2016-05-17 21:24:13 -07:00
Henrik Rydgard dc772e6f3a Add missing cases to simplify pass 2016-05-15 23:39:42 +02:00
Henrik Rydgard f544364c4a Fix bug in vus2i (thanks unknown), recognize vectors in IR disasm 2016-05-15 23:35:33 +02:00
Unknown W. Brackets 6413b44434 jit-ir: Enable IR for madd(u)/msub(u). 2016-05-14 19:23:51 -07:00
Unknown W. Brackets 4ac773e8b4 jit-ir: Implement bit reverse instruction. 2016-05-14 18:21:42 -07:00
Henrik Rydgard 0541fe36df Symbian buildfix, fix for fpu test 2016-05-14 15:26:43 +02:00
Henrik Rydgard 91bc3c31a5 Warning fixes 2016-05-14 14:01:27 +02:00
Henrik Rydgard 7a7c3b9b9f More VFPU, vmmul thoughts 2016-05-14 14:00:01 +02:00
Unknown W. Brackets efc8a8e353 Hack to make Symbian build. 2016-05-13 23:56:17 -07:00
Henrik Rydgard b7091a8f5d Simplifications and fixes 2016-05-13 21:02:23 +02:00
Henrik Rydgard 5b2504120d Optimize some common prefixes 2016-05-13 20:15:20 +02:00
Henrik Rydgard 91a6cf5e44 Add a couple more passes (2-op, optimize f<->v fp moves) 2016-05-13 20:14:03 +02:00
Henrik Rydgard f636b2a315 Minor build and other fixes 2016-05-13 19:31:27 +02:00
Unknown W. Brackets 9e3572dc63 jit-ir: Improve vidt to handle more cases. 2016-05-12 22:40:26 -07:00
Unknown W. Brackets 57b3dbff7e jit-ir: Avoid flushing on a few Vec4 ops. 2016-05-12 21:01:46 -07:00
Unknown W. Brackets 9f183c97ba jit-ir: Prevent reading ahead for each reg write. 2016-05-12 18:30:55 -07:00
Unknown W. Brackets d06c6c080c jit-ir: Expand unused regs to regular GPRs. 2016-05-12 18:30:55 -07:00
Unknown W. Brackets 99468c6fc1 jit-ir: Optimize out unused temp regs. 
This way, if constants have made the temp obsolete (common with ins, for
example), it won't even get set anymore.
 2016-05-12 18:30:53 -07:00
Henrik Rydgard 850d0abc91 IR: More VFPU. Support normal fp compares. 2016-05-12 20:16:15 +02:00
Henrik Rydgard 2cbfb192c4 IR: Lots more VFPU support, some with SIMD 2016-05-12 12:17:25 +02:00
Henrik Rydgard db1d1ff9fd IR: Merge the FPU and VFPU instruction sets, no reason to keep them apart 2016-05-10 22:55:27 +02:00
Henrik Rydgard 45efcda6b1 IR: Some more VFPU 2016-05-10 21:50:08 +02:00