Commit Graph
41 Commits
Author SHA1 Message Date
Henrik Rydgård bdce0e2e44 Buildfix: include <cfloat> for FLT_MAX in TestArm64Emitter
MSVC pulls it in transitively, gcc and clang don't - broke the gcc-normal,
clang-normal, macos and test-headless-alpine CI jobs.
2026-08-31 00:29:22 +02:00
Henrik RydgårdandClaude Opus 5 5f9131ed2b Emitters: fix a batch of encoding bugs
Found by a review pass over Common/. Three of these affect code the JITs
actually emit today:

* ARM64 TryMOVI(8) returned true unconditionally ("can always do 8"), but MOVI
  with an 8-bit element replicates imm8 into every byte, so it can only encode a
  byte-uniform value. TryAnyMOVI always tries size 8 first, so it succeeded for
  every constant. MOVI2FDUP(FLT_MAX) - VertexDecoderArm64's Jit_PosFloat - came
  out as "movi v0.16b, #0xff", a quiet NaN, and since FMINNM/FMAXNM return the
  other operand for a quiet NaN, the infinity clamp silently did nothing.
  TryAnyMOVI's replication loop was also shifting by every bit position instead
  of by multiples of the element size, and it now only tries an element size the
  value actually repeats at. Regression test added.

* RISC-V SW()'s stack-pointer compression path called C_LWSP instead of C_SWSP,
  turning a store into a load that clobbers rs2 whenever autocompress is on
  (which RiscVJit and VertexDecoderRiscV both enable).

* LoongArch64 EncodeDFj passed the raw register enum instead of DecodeReg(fj),
  so bit 10 was always set and MOVFR2GR_S emitted movfr2gr.d - live in the
  LoongArch JIT's mfc1 and its FPU/vector compilers.

The rest have no callers today, but are wrong as written:

* ARM64: MOVI/MVNI computed the MSL cmode one too high (MSL #8 is 1100, not
  1101); TryMOVI's MVNI-with-MSL branch passed the value instead of its
  complement; TBZ/TBNZ put the register size in bit 31 where b5 belongs and
  didn't mask the bit index to 5 bits; the LDR/LDRSW/PRFM literal form checked
  the wrong mask for imm19 and wrote it unmasked; FCVTZS/FCVTZU's GPR-
  destination branch skipped DecodeReg and derived the type field from the GPR
  rather than from the float source.
* LoongArch64: LDPTR_D/STPTR_W/STPTR_D all passed Opcode32::LDPTR_W;
  AMCAS_DB_D duplicated AMSWAP_DB_D's opcode; EncodeJK shifted rk by 5 instead
  of 10; BYTEPICK_D masked its shift to 2 bits instead of 3.
* x64: VGATHERDPD/VGATHERQPS/VGATHERQPD used the wrong opcode/W combinations
  (only VGATHERDPS was right).

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01DCPmm7FoQUoqrbMdhfqhQ2
2026-08-30 13:44:34 +02:00
Henrik Rydgård 8397fd6791 Also disable the GPU JIT tests on ARM64, not applicable 2024-04-29 11:13:35 +02:00
Unknown W. Brackets a7b7bf7826 Global: Set many read-only params as const.
This makes what they do and which args to use clearer, if nothing else.
2022-12-10 21:13:36 -08:00
Unknown W. Brackets 7910b4029a arm64jit: Track writable and non-writable pointers.
Switch uses different memory regions.  We can handle this, might as well
cleanup some const abuse.
2020-05-17 00:15:12 -07:00
Henrik Rydgard a1ec735f6c ARM64Emitter: Implement instructions to move data to/from SP 2017-01-26 14:23:42 +01:00
Henrik Rydgard ffe4c266ef Add CodeBlockCommon base class to remove further arch-specificity in JitBlockCache
Remove unused ArmThunk.
2016-05-01 11:40:00 +02:00
latot afeb012d04 Add missing include files to unittest 2015-10-24 13:24:05 -03:00
Henrik Rydgard 35c65973c1 ARM64 jit: implement vuc2i, vc2i, vus2i, vs2i instructions 2015-07-11 13:25:58 +02:00
Henrik Rydgard 28456bef90 ARM64: Add NEON EOR encoding 2015-07-11 12:36:44 +02:00
Henrik Rydgard 72651835c3 A bunch more ARM64 encodings (*MIN,*MAX,XTN,SHRN, etc) 2015-07-11 12:16:56 +02:00
Henrik Rydgard 937feb6892 ARM64 disasm: Fix disasm of msr/mrs 2015-07-05 11:00:23 +02:00
Henrik Rydgard b865070de1 ARM64 emitter/disasm: Fix LDNP/STNP disassembly, also fix test of smaddl 2015-07-05 09:57:58 +02:00
Unknown W. Brackets 8ea7f99072 arm64: Fix imm wasting when STP doesn't work out. 2015-07-04 07:09:47 -07:00
Jan Beich 0b66a0a03c unittest: avoid build error on case-sensitive filesystems
unittest/TestArm64Emitter.cpp:1:10: fatal error: 'Common/ARM64Emitter.h' file not found
unittest/TestX64Emitter.cpp:1:10: fatal error: 'Common/X64Emitter.h' file not found
2015-05-28 06:02:59 +00:00
Henrik Rydgård 39be916d8a ARM64: More emitter/disasm 2015-04-06 18:13:44 +02:00
Henrik Rydgård 459ba28655 ARM64: SW skinning runs without crashing but is broken. 2015-04-06 18:13:44 +02:00
Henrik Rydgård f82b613371 ARM64 emitter/disasm: Implement ASIMD LDP/STP instructions 2015-04-06 18:13:42 +02:00
Henrik Rydgård 013bbc71af ARM64: Fix DUP disasm, INS disasm 2015-04-06 18:13:40 +02:00
Henrik Rydgård a3db3ed5c1 ARM64 emitter: Fix UXTL/SXTL and friends. Add disasm. 2015-04-06 18:13:40 +02:00
Henrik Rydgård 853d6ea34b ARM64 emitter: Add FMLA/FMLS vector versions 2015-04-06 18:13:39 +02:00
Henrik Rydgård 065cd97dc2 ARM64: LLVM buildfix, some more disasm 2015-04-06 18:13:39 +02:00
Henrik Rydgard 7d918c0ad8 ARM64: Just some disasm improvements 2015-04-06 18:13:35 +02:00
Henrik Rydgard ad3d539451 ARM64: Attempt at lwl/lwr/swl/swr. The first two don't work 2015-04-06 18:13:35 +02:00
Henrik Rydgard 4618275f99 ARM64: Add a few aliases to emitter. Disasm fixes. 2015-04-06 18:13:33 +02:00
Henrik Rydgard acf08eefa8 ARM64: Fix FCVTL, use it in v2hf 2015-04-06 18:13:33 +02:00
Henrik Rydgard 0849e270ee ARM64: fmla encoding, more disasm 2015-04-06 18:13:31 +02:00
Henrik Rydgard 9c79831237 ARM64 emitter: Fix FP immediates 2015-04-06 18:13:29 +02:00
Henrik Rydgard 9a5a093105 ARM64 emitter/disasm: More scalar FPU instructions 2015-04-06 18:13:27 +02:00
Henrik Rydgard 6cb107d6fc ARM64: Fix LDP disassembly 2015-04-06 18:13:25 +02:00
Henrik Rydgard 5a5f3c94fd ARM64: Guess what? more emitter & disasm 2015-04-06 18:13:24 +02:00
Henrik Rydgard 0f430e6cd1 ARM64: More asimd scalar disasm, encoding fix 2015-04-06 18:13:23 +02:00
Henrik Rydgard 9f689b871a ARM64: Work on emitting and disassembling fp conversion ops 2015-04-06 18:13:22 +02:00
Henrik Rydgard 2566972a4d ARM64: Further disasm work 2015-04-06 18:13:21 +02:00
Henrik Rydgard 120e0bba3c ARM64: Disassemble csel and multiply instructions 2015-04-06 18:13:19 +02:00
Henrik Rydgard acd9502b44 ARM64: stp/ldp disasm improvements 2015-04-06 18:13:17 +02:00
Henrik Rydgard 5dff3f8c89 ARM64: Implement scalar FMOV. This makes the FPU2op ops work. 2015-04-06 18:13:16 +02:00
Henrik Rydgard 4233921ab7 ARM64: Some more instructions, func replacements 2015-04-06 18:13:16 +02:00
Henrik Rydgard 77501e220d ARM64: Enable a few more instructions, more emitter/disasm unittests 2015-04-06 18:13:13 +02:00
Henrik Rydgard cc722f09f6 Improve ARM64 disassembly by merging MOVZ+MOVK. Minor stuff. 2015-04-06 18:13:07 +02:00
Henrik Rydgard 8945b2476d Add the beginnings of a rudimentary ARM64 disassembler 2015-04-06 18:13:03 +02:00