preserve-emulation/ppsspp
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f03cd0b2ad88f89d3ccae8fc07fca362eaac8e47
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10 Commits
Author SHA1 Message Date
Henrik Rydgård d6cdb6e5d9 Merge pull request #17900 from unknownbrackets/irjit-vsgelt 
irjit: Implement vsge/vslt
 2023-08-13 19:59:14 +02:00
Unknown W. Brackets 2b36e0a625 irjit: ZeroFpCond -> FpCondFromReg. 
We already have a zero reg, so this is more useful and symmetrical.
 2023-08-13 10:40:47 -07:00
Unknown W. Brackets 81f67c717c riscv: Fix block link for prev blocks. 
Oops, was just reversed so never linking.
 2023-08-12 10:48:39 -07:00
Unknown W. Brackets fcc90095f7 riscv: Enable block linking. 2023-08-12 09:37:02 -07:00
Unknown W. Brackets b3cdf06c5a riscv: Write fixup on block invalidation. 2023-08-12 09:37:02 -07:00
Unknown W. Brackets 3757ebca2d irjit: Invalidate/finalize target blocks. 
Doesn't actually do anything yet, but adds plumbing.
 2023-08-12 09:37:02 -07:00
Unknown W. Brackets ad4cbbab8e riscv: Don't cache mipState on backend. 
Bad sign if we're trying to use it, anyway.
 2023-08-08 23:17:32 -07:00
Unknown W. Brackets 79ca880ac7 irjit: Implement vqmul, add Vec4Blend. 
Should be useful more places.
 2023-08-06 13:38:00 -07:00
Unknown W. Brackets 93e3d35f5d irjit: Move more to IRNativeBackend, split. 2023-08-06 00:16:43 -07:00
Unknown W. Brackets 691799a0ca irjit: Centralize native jit compile dispatch. 2023-08-03 23:14:58 -07:00