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e46bd61e2eccbf1fb5d1e12cc73d58be643bc5dc
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70 Commits
Author SHA1 Message Date
Henrik RydgårdandClaude Opus 5.5 ae32477764 Core: Let 16-bit CPU accesses through the depth mirrors see the GE's layout 
With the software renderer, which now stores depth as the GE does, a
16-bit read or write at VRAM's 0x04200000 or 0x04600000 mirror goes to
where the GE's 16-bit or 32-bit color layout puts that depth pixel
(ppsspp-re geprobe exp88: the mirrors are the layout's exact inverse).
Games access depth there with nothing else, so other widths stay plain.

The accessors check the address, then whether the GPU core is the
software renderer (CoreParameter); the hardware renderers keep depth plain
and handle the layout their own way. The renderer keeps the layouts up to
date with the EDRAM address translation. With it, the JITs send 16-bit
loads and stores to the interpreter, and the IR passes don't change a
load's width to or from 16 bits.
The pspautotests that read depth through the mirrors now do so 16 bits
at a time, re-recorded on hardware unchanged.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
 2026-10-08 18:37:23 +02:00
Henrik Rydgård a810597ac0 Implement MMIO for the JIT (by falling back to the interpreter for load/stores from kernel addresses) 
Fixes the VSH in JIT mode (but NOT ir)
 2026-08-25 00:22:40 +02:00
Unknown W. Brackets df2462b1d9 irjit: Implement ll/sc. 
These occur more than I expected in LittleBigPlanet while loading.
 2023-07-29 17:57:44 -07:00
Unknown W. Brackets 6df939034a Core: Cleanup some sign extensions for clarity. 2023-04-05 17:16:51 -07:00
Unknown W. Brackets d3c06266c5 jit: Fix conditional disable flags. 2021-01-09 11:50:32 -08:00
Henrik Rydgård 4c034ce988 Make all the Comp_Cache implementations the same. 
We have the informative comments in the interpreter implementation
anyway.
 2020-10-16 09:13:41 +02:00
Henrik Rydgård c5e0b799d9 Remove category from _assert_msg_ functions. We don't filter these by category anyway. 
Fixes the inconsistency where we _assert_ didn't take a category but
_assert_msg_ did.
 2020-07-19 20:33:25 +02:00
Henrik Rydgård c80dd44da8 ARM/ARM64: Ignore invalid immediate addresses in delay slots, which may be conditional. 
Should do something in x86's safe mem too, but leaving for later.

Replaces #11824
 2019-02-23 10:15:09 +01:00
Unknown W. Brackets 419c1fbd73 Jit: Respect flags for jit types and features. 
Left some free space for more.
 2019-02-03 14:57:08 -08:00
Unknown W. Brackets 5510a69d41 armjit: Enable breakpoints. 2018-06-06 17:31:56 -07:00
Henrik Rydgård ed776d8c0b ARM: Delete obsolete comments and check 2017-08-18 13:48:11 +02:00
Florent Castelli 8c3552de74 cmake: Detect features at compile time 
Instead of relying on manually passed down flags from CMake,
we now have ppsspp_config.h file to create the platform defines for us.
This improves support for multiplatform builds (such as iOS).
 2016-10-19 12:31:19 +02:00
Henrik Rydgard dc2f6a30fb ARM64: Fix joining of lwl/lwr and swl/swr. "implement" the cache instruction. 2015-07-11 16:25:22 +02:00
Henrik Rydgård a897723e6a Separate out jit reading nearby instructions. 
This makes it easier to use an IR for these things, or remove them.
 2015-04-11 00:53:24 -07:00
Henrik Rydgard 05a8e2e35d Some work towards being able to build two JITs together 
This will be useful for testing/debugging, but not there yet.
 2014-12-13 21:13:54 +01:00
Henrik Rydgard 51d55bd645 Namespacing cleanup (it's bad to do "using namespace" in a header) 2014-12-07 14:44:15 +01:00
Henrik Rydgard 4457dca4c9 Rename the ARM Jit class to ArmJit 2014-12-07 14:25:22 +01:00
Unknown W. Brackets f6f943de63 jit: MAP_NOINIT should always mean MAP_DIRTY. 2014-11-29 00:14:08 -08:00
Unknown W. Brackets 5a89c17cf0 armjit: Allow R1 in regalloc, use LR as temp. 
LR should be safe, although it may make stack traces not work within jit,
they don't really tend to work anyway.
 2014-03-28 18:38:38 -07:00
Unknown W. Brackets ca0a8d0269 armjit: fix lwl/lwr from an imm address. 
Can't skip loading the reg value.  Likely cause of #5057, possibly other
bugs as well.
 2014-03-13 00:23:00 -07:00
Henrik Rydgård b2260149ae ARM Jit: Avoid materializing some unnecessary immediates in loads/stores 2014-03-03 14:33:22 +01:00
Henrik Rydgard 5a02ea9ff4 Fix cache instruction on ARM 2013-12-10 13:26:32 +01:00
Unknown W. Brackets 98fb2e0402 armjit: Refer to R11 as MEMBASEREG for clarity. 2013-11-14 23:37:48 -08:00
Unknown W. Brackets 67eaa2fd1c armjit: Optimize immediate load/stores in a row. 2013-11-10 16:32:48 -08:00
Unknown W. Brackets 7e46ee0b0f armjit: Replace MOVI2R with using the regcache. 
So that it can optimize the value with existing imms.

Not actually optimizing yet.
 2013-11-10 15:50:45 -08:00
Unknown W. Brackets 455a7e090d Compile the cache instruction to nothing. 
Was showing up in a few profiles, does nothing currently.
 2013-11-10 14:38:10 -08:00
Unknown W. Brackets b2c2a87511 Fix omitted CC_AL reset, fixes #4498. 
Was breaking non-fastmem lwl/lwr/etc.
 2013-11-10 09:24:40 -08:00
Unknown W. Brackets 3aa8706ae7 armjit: Optimize lwl/lwr against an imm address. 2013-11-09 08:43:48 -08:00
Unknown W. Brackets 4026944b02 armjit: Handle lwl/lwr (not pretty, though.) 2013-11-09 08:42:30 -08:00
Unknown W. Brackets cb3bb73148 armjit: Improve GPR typesafety. 2013-11-09 08:24:15 -08:00
Henrik Rydgard 502f772856 Add experimental mode to cache pointers in the arm jit. 
Turned off for now as it needs more work but seems quite promising already.
 2013-11-09 17:15:30 +01:00
Henrik Rydgard 309f904c0c Extract JitState into its own header (arm/x86) 2013-11-08 18:51:52 +01:00
Henrik Rydgard 32c95af820 ARM: Some zero-register fixes 2013-11-07 15:29:13 +01:00
Unknown W. Brackets 157b682344 Always use fastmem for sw/lw on SP. 2013-09-07 22:44:18 -07:00
Unknown W. Brackets 97aa1a631e Improve typesafety in the x86 regalloc. 2013-08-24 19:41:10 -07:00
Unknown W. Brackets 109ad17ac6 Use a typesafe struct for opcodes. 
Also, correctly read delayslots using Read_Instruction on ARM.
 2013-08-24 15:36:24 -07:00
Unknown W. Brackets 1ed8edb0d3 Avoid some dangerous hex constant widths. 2013-08-22 23:23:48 -07:00
Unknown W. Brackets 796d2c10c6 armjit: VRAM comes before RAM, fix slowmem check. 
Can't think of anything else, hopefully fixes #1021.
 2013-03-18 08:08:40 -07:00
Unknown W. Brackets b8eb526691 armjit: improve slowmem, fix vram check. 
Darn, copy/paste error.
 2013-03-16 20:31:51 -07:00
Unknown W. Brackets 6ef5f4c8dc armjit: Refactor slowmem path for reusing it. 2013-03-16 14:37:35 -07:00
Unknown W. Brackets 45b0b1203f armjit: No, LDR/STR do not update flags. 
Oops, had some other bug and thought this was the issue.
 2013-03-16 14:37:35 -07:00
Unknown W. Brackets de3713fc50 armjit: improve mem speed without fastmem. 2013-03-16 14:37:35 -07:00
Unknown W. Brackets 8f3904d32d armjit: Speed up imm addresses in slowmem mode. 2013-03-16 14:37:35 -07:00
Sacha 529803e429 Sonic's ArmEmitter changes (cross-project merge from Dolphin) 2013-03-14 12:47:29 +10:00
Sacha 8125d96ce1 Small update for shifted load/stores. Still disabled. 2013-03-07 01:04:41 +10:00
Sacha a8b6fca61b Separate codepaths for shifted load/stores and normal load/stores. Fix dirty regs. 2013-03-07 00:59:07 +10:00
Sacha ae3b881a7f Use correct args for Operand2(..) through armjit. Fix STR(..). 2013-03-07 00:59:07 +10:00
Sacha 268d16bd24 Use correct args for STR(..) throughout armjit. 2013-03-07 00:59:07 +10:00
Sacha 23fb88c5fe Enable optimisation codepath (left+right combines). 2013-03-07 00:59:07 +10:00
Henrik Rydgard 9f327985fc armjit: disable lwl/lwr/swl/swr 2013-03-05 23:09:26 +01:00