Commit Graph
53 Commits
Author SHA1 Message Date
Henrik RydgårdandClaude Opus 5 5f9131ed2b Emitters: fix a batch of encoding bugs
Found by a review pass over Common/. Three of these affect code the JITs
actually emit today:

* ARM64 TryMOVI(8) returned true unconditionally ("can always do 8"), but MOVI
  with an 8-bit element replicates imm8 into every byte, so it can only encode a
  byte-uniform value. TryAnyMOVI always tries size 8 first, so it succeeded for
  every constant. MOVI2FDUP(FLT_MAX) - VertexDecoderArm64's Jit_PosFloat - came
  out as "movi v0.16b, #0xff", a quiet NaN, and since FMINNM/FMAXNM return the
  other operand for a quiet NaN, the infinity clamp silently did nothing.
  TryAnyMOVI's replication loop was also shifting by every bit position instead
  of by multiples of the element size, and it now only tries an element size the
  value actually repeats at. Regression test added.

* RISC-V SW()'s stack-pointer compression path called C_LWSP instead of C_SWSP,
  turning a store into a load that clobbers rs2 whenever autocompress is on
  (which RiscVJit and VertexDecoderRiscV both enable).

* LoongArch64 EncodeDFj passed the raw register enum instead of DecodeReg(fj),
  so bit 10 was always set and MOVFR2GR_S emitted movfr2gr.d - live in the
  LoongArch JIT's mfc1 and its FPU/vector compilers.

The rest have no callers today, but are wrong as written:

* ARM64: MOVI/MVNI computed the MSL cmode one too high (MSL #8 is 1100, not
  1101); TryMOVI's MVNI-with-MSL branch passed the value instead of its
  complement; TBZ/TBNZ put the register size in bit 31 where b5 belongs and
  didn't mask the bit index to 5 bits; the LDR/LDRSW/PRFM literal form checked
  the wrong mask for imm19 and wrote it unmasked; FCVTZS/FCVTZU's GPR-
  destination branch skipped DecodeReg and derived the type field from the GPR
  rather than from the float source.
* LoongArch64: LDPTR_D/STPTR_W/STPTR_D all passed Opcode32::LDPTR_W;
  AMCAS_DB_D duplicated AMSWAP_DB_D's opcode; EncodeJK shifted rk by 5 instead
  of 10; BYTEPICK_D masked its shift to 2 bits instead of 3.
* x64: VGATHERDPD/VGATHERQPS/VGATHERQPD used the wrong opcode/W combinations
  (only VGATHERDPS was right).

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01DCPmm7FoQUoqrbMdhfqhQ2
2026-08-30 13:44:34 +02:00
xiaofan 885f078bb7 Fix RiscVEmitter::QuickFLI (#20351)
using `fmv.w.x` intead of `fmv.d.x` when load Float32 to float register

Signed-off-by: xiaofan <xiaofan@iscas.ac.cn>
2025-05-17 13:46:18 +08:00
Henrik Rydgård e01ca5b057 Logging API change (refactor) (#19324)
* Rename LogType to Log

* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.

* Mac/ARM64 buildfix

* Do the same with the hle result log macros

* Rename the log names to mixed case while at it.

* iOS buildfix

* Qt buildfix attempt, ARM32 buildfix
2024-07-14 14:42:59 +02:00
Unknown W. Brackets 52db66e7ad riscv: Add vector bitmanip encoding. 2023-12-29 09:42:23 -08:00
Unknown W. Brackets 83dc1c9705 riscv: Add detect flags, not detected yet. 2023-12-29 09:42:23 -08:00
Unknown W. Brackets e5467d2706 riscv: Add czero instruction encoding. 2023-12-29 09:42:23 -08:00
Unknown W. Brackets e3c6add63a riscv: Add encoding for Zcb. 2023-12-29 09:42:23 -08:00
Unknown W. Brackets 15cb782f85 riscv: Implement Zfa encoding.
Not yet enabled/detected.
2023-12-29 09:42:23 -08:00
Unknown W. Brackets fc476020ba riscv: Improve immediate generation.
Use compressed instructions more, better jumps when outside PC 32-bit
range.
2023-08-12 09:37:02 -07:00
Unknown W. Brackets 4b9011e475 riscv: Reduce call bloat using temps. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets 26a527bdf8 riscv: Implement float/int conversion. 2023-07-30 00:45:51 -07:00
Unknown W. Brackets 76e3246065 riscv: Reduce jit codesize a bit. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 47b81985bd riscv: Initial untested dispatcher.
The minimum to actually, probably, running code.  Pretty slow.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets 030a27f15d riscv: Stop considering bitmanip "B".
Apparently it's not being called B anymore and B is still reserved.
2023-07-23 14:41:08 -07:00
Unknown W. Brackets e0eace505b riscv: Fix cases of SetRegToImmediate().
Was using the wrong value for AUIPC, causing assertion failures and wrong
values.  Also needed to handle sign-extend more carefully.
2023-07-23 14:41:08 -07:00
Unknown W. Brackets 27e60a9f2e riscv: Sum weighted matrices in vertexjit.
Not yet doing pos/norm, so not used yet.
2023-02-16 18:32:58 -08:00
Unknown W. Brackets 04ce3a0572 riscv: Allow subset of B extension to be used. 2023-02-16 16:09:22 -08:00
Unknown W. Brackets 684aa75388 riscv: Include morph in vertexjit. 2023-02-14 20:20:55 -08:00
Unknown W. Brackets 1ec33ddc04 riscv: Use __riscv_flush_icache() on Linux.
This seems to perhaps clear icache on all harts.  Otherwise crashing is
seen.  Not sure what to do on other platforms.
2023-02-14 19:59:42 -08:00
Unknown W. Brackets 0b05d20c0a riscv: Fix poison with compressed instructions. 2023-02-12 13:02:55 -08:00
Unknown W. Brackets 89c18d8077 riscv: Cleanup missing Poison, Crash. 2023-02-12 12:10:29 -08:00
Unknown W. Brackets a0ef9ce103 riscv: Add half-float encodings.
These are simple.
2023-01-29 16:31:01 -08:00
Unknown W. Brackets dcd83c1e47 riscv: Detect Zicsr with cpu_features. 2023-01-29 15:24:41 -08:00
Unknown W. Brackets 3bc2450b5e riscv: Add bitmanip instructions to emitter (#16832)
* riscv: Cleanup emitter, add bitmanip detect.

Better to encode using Funct7::ZERO, and obviously for SRA.

* riscv: Add bitmanip instructions to emitter.
2023-01-22 21:37:47 +01:00
Unknown W. Brackets 2aeee83971 riscv: Add vector transfer instructions. 2023-01-22 00:17:40 -08:00
Unknown W. Brackets c99eb18f33 riscv: Add vector mask instructions. 2023-01-21 23:43:28 -08:00
Unknown W. Brackets 88de043329 riscv: Add vector reduce instructions. 2023-01-21 22:35:38 -08:00
Unknown W. Brackets 2a7bdbf802 riscv: Add vector float move/compare/unary. 2023-01-21 22:05:13 -08:00
Unknown W. Brackets f0796676fd riscv: Add vector float arith/mul funcs.
Including all the fused multiplies.
2023-01-21 20:48:49 -08:00
Unknown W. Brackets a1ca291362 riscv: Add vector fixed-point arith instructions. 2023-01-21 20:23:10 -08:00
Unknown W. Brackets a313e440b4 riscv: Add vector integer move/broadcast. 2023-01-21 19:46:50 -08:00
Unknown W. Brackets 6f78f2a2d2 riscv: Add vector integer muliplies. 2023-01-21 19:46:34 -08:00
Unknown W. Brackets b3be901557 riscv: Add vector bitwise/compare funcs. 2023-01-21 19:36:22 -08:00
Unknown W. Brackets 6fa50eaa82 riscv: Add vector int add/sub and many encodings. 2023-01-21 19:36:11 -08:00
Unknown W. Brackets bfd60a67ad riscv: Add vector load/store ops. 2023-01-21 19:36:11 -08:00
Unknown W. Brackets 82f0502b4e riscv: Implement CPU feature detection. 2022-12-21 03:12:16 +00:00
Unknown W. Brackets 5916b3f3a8 riscv: Fix compile error on clang.
This also works on gcc.
2022-12-21 03:07:47 +00:00
Unknown W. Brackets 1810692236 Global: Cleanup some type/range checks. 2022-12-10 21:13:37 -08:00
Sprite 0ed86188b0 Fix const pointer conversion error for RISC-V 2022-09-15 23:53:19 +08:00
Unknown W. Brackets 08d82ec15b riscv: Emit compressed instructions.
Includes automatically using compressed, optionally.
2022-08-27 15:44:19 -07:00
Unknown W. Brackets 946080206d riscv: Improve sign reduce/immediate readability. 2022-08-27 15:44:18 -07:00
Unknown W. Brackets c807d459f6 riscv: Emit ADD/SUB/etc. for ADDW/SUBW/etc. on R32.
No need to complicate code, we can just write ADDW() and expect it to work
on R32 (if ever motivated to support it.)
2022-08-27 15:44:18 -07:00
Unknown W. Brackets c81d887a86 riscv: Include an LI helper in the emitter.
Can be used for integers and floats.
2022-08-27 15:44:18 -07:00
Unknown W. Brackets 4a93647acb riscv: Emit CSR manipulation instructions. 2022-08-25 21:20:49 -07:00
Unknown W. Brackets b5755b6cf7 riscv: Validate FixupBranch usage better.
Also avoid FixupBranch alignment issues.
2022-08-25 21:20:49 -07:00
Unknown W. Brackets 591de6be1d riscv: Emit float instructions. 2022-08-25 21:19:28 -07:00
Unknown W. Brackets 53693072d2 riscv: Emit atomic operations. 2022-08-25 21:19:28 -07:00
Unknown W. Brackets c66d02d4db riscv: Emit mul/div instructions. 2022-08-25 21:19:28 -07:00
Unknown W. Brackets 00280ab2ad riscv: Emit fence and 64-bit instructions. 2022-08-25 21:19:28 -07:00
Unknown W. Brackets 49ec8a207d riscv: Emit 32-bit 3-op instructions, validate GPR. 2022-08-25 21:19:27 -07:00