Commit Graph
24 Commits
Author SHA1 Message Date
Henrik Rydgård 98e8ffe7cd Check framebuffer copy sources, and fix two easy crashes
The three framebuffer upload paths took Memory::GetPointerUnchecked() on a
GE-supplied source address and then read height rows of it, without ever checking
that span was mapped. Only the destination was validated (and DoBlockTransfer's own
memcpy is carefully guarded, so the intent was clearly there). A copy whose source
starts near the end of RAM walks straight off the end of the view. Clamp the row
count to what's actually mapped, and warn when we do.

GhidraClient dereferenced getArray()->value for both "symbols" and "types" without a
null check, and the getTag() test underneath could never catch it - getArray() has
already filtered by tag, so it returns either a JSON_ARRAY node or nullptr. Any
HTTP 200 that parses as JSON but isn't the shape we expect - {}, a bare array, an
incompatible ghidra-rest-api, or the host/port pointed at some other JSON service -
crashed the worker thread. FetchTypes() runs first, so that's the one you'd hit.

RiscV and LoongArch CPU detection divided TotalLogicalCount() by ProcessorCount()
before checking it. ProcessorCount() returns 0 whenever /proc/cpuinfo can't be read
or doesn't parse, which is SIGFPE during static init of the cpu_info global - before
anything could handle it. The existing <= 0 guard sat after the division.

314 pspautotests pass; frametests show the same 3 pre-existing failures as master.
2026-08-31 12:15:50 +02:00
Henrik Rydgård 5751e202a5 Remove redundant .c_str() 2025-08-31 13:37:43 +02:00
Mark Zhuang 037e89fdd1 RISCV: enable some cpu extensions for spacemit k1
spacemit vendor linux kernel is spacemit,k1-x:
k1-x is from spacemit https://gitee.com/bianbu-linux/linux-6.6/blob/k1-bl-v2.1.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi#L17
while upstream linux kernel is spacemit,k1:
https://github.com/torvalds/linux/blob/a5806cd506af5a7c19bcd596e4708b5c464bfd21/arch/riscv/boot/dts/spacemit/k1.dtsi#L11
2025-05-20 16:11:42 +08:00
Brad Smith e1916bf1fe CMake: Add checks for getauxval and elf_aux_info
Add support for CPU feature detection on OpenBSD and FreeBSD riscv64.
2025-01-26 22:44:04 -05:00
Brad Smith 59ba9ab973 Fix building on OpenBSD/riscv64.
Unbreak on riscv64, we don't have sys/auxv.h or getauxval().

OpenBSD/riscv64 assumes RV64GC, aka RV64IMAFDC.

Our kernel provides no support for the V extension.
2024-04-27 07:44:37 -04:00
Henrik Rydgård 1f129b6dca Replace "ReadFileToString" with a few semantically clearer wrappers. 2024-01-25 09:55:54 +01:00
Henrik Rydgård 46b25d20a4 Merge pull request #18637 from unknownbrackets/riscv-more
Add some more RISC-V extensions to emitter
2023-12-29 19:03:49 +01:00
Unknown W. Brackets 52db66e7ad riscv: Add vector bitmanip encoding. 2023-12-29 09:42:23 -08:00
Unknown W. Brackets 83dc1c9705 riscv: Add detect flags, not detected yet. 2023-12-29 09:42:23 -08:00
Henrik Rydgård e3177ac870 Make some global string pointers const, not just the strings.
Minor cleanup.
2023-12-29 14:09:45 +01:00
Unknown W. Brackets 030a27f15d riscv: Stop considering bitmanip "B".
Apparently it's not being called B anymore and B is still reserved.
2023-07-23 14:41:08 -07:00
Unknown W. Brackets 0c99d6d3fa riscv: Workaround Zicsr detection issue. 2023-07-23 14:41:08 -07:00
Unknown W. Brackets ac40721a64 riscv: Use cpu_features for V detection. 2023-04-29 10:07:50 -07:00
Unknown W. Brackets 63f370916b riscv: Enable Zba/Zbb by soc compatible.
Instead of u74, because apparently some older u74 don't support it.
2023-03-03 03:37:58 +00:00
Unknown W. Brackets 04ce3a0572 riscv: Allow subset of B extension to be used. 2023-02-16 16:09:22 -08:00
Unknown W. Brackets dcd83c1e47 riscv: Detect Zicsr with cpu_features. 2023-01-29 15:24:41 -08:00
Unknown W. Brackets 09eb509df4 Common: Expose CPU extension list directly.
A bit silly to rely on the specific string formatting of a summary.
2023-01-29 15:13:44 -08:00
Unknown W. Brackets 3bc2450b5e riscv: Add bitmanip instructions to emitter (#16832)
* riscv: Cleanup emitter, add bitmanip detect.

Better to encode using Funct7::ZERO, and obviously for SRA.

* riscv: Add bitmanip instructions to emitter.
2023-01-22 21:37:47 +01:00
Unknown W. Brackets 82f0502b4e riscv: Implement CPU feature detection. 2022-12-21 03:12:16 +00:00
Pierce Andjelkovic 9ac4931636 Fix get CPU & CPU Brand 2021-07-31 03:03:13 +10:00
Pierce Andjelkovic bd8759853b Fix ABI 2021-07-31 01:50:48 +10:00
Pierce Andjelkovic 0d0e2c44e0 Fix copied mips bugs 2021-07-29 07:47:09 +10:00
Pierce Andjelkovic d452b0c1f7 No CPU part for RISC-V 2021-07-29 03:26:18 +10:00
Pierce Andjelkovic d9a3741fcb RISC-V CPU detect 2021-07-28 21:58:56 +10:00