13 Commits

Include renames

Author	SHA1	Message	Date
Unknown W. Brackets	161465ab66	riscv: Centralize register FlushAll().	2023-08-19 21:30:03 -07:00
Unknown W. Brackets	92f7374c89	riscv: Centralize reg mapping itself.	2023-08-19 16:15:49 -07:00
Unknown W. Brackets	4e41f83ecc	riscv: Centralize IR reg cache metadata checks. ... These are all largely the same between backends.	2023-08-17 23:03:31 -07:00
Unknown W. Brackets	ebab0e1591	riscv: Centralize reg allocation.	2023-08-17 18:50:33 -07:00
Unknown W. Brackets	b30daa5760	riscv: Centralize state of regcaches.	2023-08-15 21:51:38 -07:00
Unknown W. Brackets	1a92027810	riscv: Make Vec4Shuffle overlap safe.	2023-08-08 23:00:45 -07:00
Unknown W. Brackets	f870271011	riscv: Spill registers more intelligently.	2023-07-30 14:24:12 -07:00
Unknown W. Brackets	020706f545	riscv: Implement float saturate clamping.	2023-07-30 14:24:12 -07:00
Unknown W. Brackets	6b632a103d	riscv: Implement FSin/similar.	2023-07-29 19:02:15 -07:00
Unknown W. Brackets	4e17c59cc2	riscv: Implement simple vec4 ops via floats.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	7071884a47	riscv: Handle rounding mode and ctrl transfers.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	067a033dc0	riscv: Add FPU regcache.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	4c1cc2dfdc	riscv: Add a register cache for jit. ... Not yet actually used. Might be buggy.	2023-07-23 18:01:00 -07:00