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Author SHA1 Message Date
shenweip 0a9cf9b1bc Turn up logging. 2013-11-10 10:40:56 +08:00
raven02 7c6a4cf87e Attempt for another matching framebuffer logic 2013-11-10 10:38:33 +08:00
Henrik Rydgård 345a4ccf0e Merge pull request #4487 from unknownbrackets/perf 
Texture cache hashing tweaks, disable second cache on mobile
 2013-11-09 17:30:40 -08:00
Henrik Rydgård bcd499ff38 Merge pull request #4489 from sum2012/patch-2 
Attempt to fix Colin Mcrae Dirt 2 Crash correctly
 2013-11-09 17:30:25 -08:00
Igor Calabria 33f4b44061 Moves proAdhoc extra functions to a separate file 2013-11-10 01:26:31 +00:00
sum2012 e4b68099e0 Attempt to fix Colin Mcrae Dirt 2 Crash correctly 
#4482
 2013-11-10 08:23:31 +08:00
Unknown W. Brackets b310edc5f8 Fix typo in ARM debug build. 2013-11-09 15:58:27 -08:00
Unknown W. Brackets fa79d7f13c Handcode the non-NEON texcache hash as well on ARM. 
Well, it could be a better algorithm, but at least this uses LDMIA.
 2013-11-09 14:51:23 -08:00
Unknown W. Brackets 2dfa2379f4 Rewrite QuickTexHashNEON directly in asm. 
Seems like gcc couldn't optimize it to this.
 2013-11-09 12:54:55 -08:00
Unknown W. Brackets 3f57f1f447 Disable the secondary texcache on mobile. 
It helps in games like Final Fantasy 2 and Popolocrois, but it seems to
cause out of memory errors despite the checks.
 2013-11-09 12:52:58 -08:00
Henrik Rydgard d1c012d75e ARM: Open up all 32 accessible VFP registers if NEON is available. 2013-11-09 20:18:20 +01:00
Henrik Rydgård 70a239ba47 Merge pull request #4486 from unknownbrackets/debugger 
Use a shortcut for copying instructions, enable G3D log always
 2013-11-09 11:08:12 -08:00
Unknown W. Brackets 712b582d26 Remove coreParam.disableG3Dlog and enableDebugging. 
One was uninitialized, the other one unused.
 2013-11-09 11:02:12 -08:00
Unknown W. Brackets 3771ec1959 Use Ctrl-C/Ctrl-Insert to copy in disasm. 
This means trading Ctrl-C (was find again) for F3.  Also made Ctrl-F find
as well as Ctrl-S.
 2013-11-09 10:57:43 -08:00
Henrik Rydgard 497915141b Revert to normal for loop in the index generator, the < 3 case gets taken care of properly. Just existing caused some issues. 2013-11-09 19:33:40 +01:00
Henrik Rydgard 0a844ce98d Delete functions for vsge and vslt, these have been rolled into VecDo3 2013-11-09 19:29:52 +01:00
Henrik Rydgård ed6190fd24 Merge pull request #4485 from sum2012/patch-1 
Fix Colin Mcrae Dirt 2 Crash
 2013-11-09 10:25:11 -08:00
sum2012 886fcdd0b1 Fix Colin Mcrae Dirt 2 Crash 
#4482
 2013-11-10 02:23:22 +08:00
Henrik Rydgard 63334698e1 Add temporary setting to disable the vertex decoder jit while we debug it 2013-11-09 18:16:26 +01:00
Henrik Rydgård 6bc2df051e Merge pull request #4484 from unknownbrackets/armjit-ops 
Implement some more ops in armjit (divu, lwl, lwr, msub, msubu)
 2013-11-09 08:58:32 -08:00
Unknown W. Brackets a3a061a69f armjit: Optimize a division by a power of two. 
These really happen.
 2013-11-09 08:43:53 -08:00
Unknown W. Brackets 1776c85882 armjit: Implement a software divide for divu. 
It's not actually that much code.
 2013-11-09 08:43:52 -08:00
Unknown W. Brackets b2a240d105 armjit: Implement msub/msubu. 2013-11-09 08:43:52 -08:00
Unknown W. Brackets 3aa8706ae7 armjit: Optimize lwl/lwr against an imm address. 2013-11-09 08:43:48 -08:00
Unknown W. Brackets 83fe874dcc armjit: Use multiple BICs in ANDI2R if possible. 
Rather than a temporary.
 2013-11-09 08:42:31 -08:00
Unknown W. Brackets 4026944b02 armjit: Handle lwl/lwr (not pretty, though.) 2013-11-09 08:42:30 -08:00
Henrik Rydgård e90f7f360d Merge pull request #4480 from unknownbrackets/perf 
Flush regs using STMIA if possible, plus imm adjustments (armjit)
 2013-11-09 08:41:25 -08:00
Henrik Rydgard 06ce01ea04 Remove erroneous comment. 2013-11-09 17:34:52 +01:00
Unknown W. Brackets 54168b173e armjit: Clean up some magic numbers. 2013-11-09 08:25:08 -08:00
Unknown W. Brackets 6038d96b46 armjit: Flush regs using STMIA where possible. 2013-11-09 08:25:07 -08:00
Unknown W. Brackets e686ff59bf armjit: Allocate regs in preferred slots. 
This may allow better flushing.  Not sure if these are the best regs,
but if they aren't it shouldn't really hurt.
 2013-11-09 08:25:07 -08:00
Unknown W. Brackets cb3bb73148 armjit: Improve GPR typesafety. 2013-11-09 08:24:15 -08:00
Unknown W. Brackets 945b8bf5c5 armjit: optimize reverse subtract, avoid temp imms. 
If we have a non-op2 imm, get rid of it asap.  If we have a op2 friendly
imm, keep it.
 2013-11-09 08:18:43 -08:00
Unknown W. Brackets 415f22ecac armjit: Preserve imms on min/max as well. 2013-11-09 08:18:43 -08:00
Henrik Rydgard 502f772856 Add experimental mode to cache pointers in the arm jit. 
Turned off for now as it needs more work but seems quite promising already.
 2013-11-09 17:15:30 +01:00
Henrik Rydgard 58c39a38ee ARM regcache: Add mechanism to keep registers converted to pointers around 2013-11-09 16:57:29 +01:00
Henrik Rydgard 5ad04a23f4 x86 jit: Rename BindToRegister to MapReg 2013-11-09 15:23:31 +01:00
Henrik Rydgard d26692ef92 Fix bug from a couple of commits ago in ARMJit 2013-11-09 15:22:39 +01:00
Henrik Rydgard 316d23d4cc Optimize mfv/mtv/mfc1/mtc1 on x86 too 2013-11-09 14:06:45 +01:00
Henrik Rydgard 04451623b9 This variant didn't seem to make much difference either (see prev commit) 2013-11-09 13:06:10 +01:00
Henrik Rydgard 15bc5a8db7 Add small ARM perf experiment. Did not help on ARMv7 so turned it off. 
xsacha might want to try it on ARMv6.
 2013-11-09 12:57:07 +01:00
Henrik Rydgard 2fe898cda8 Add comment with link to important github thread about sceSas threading 2013-11-09 02:05:28 +01:00
Henrik Rydgård d04415ac5d Merge pull request #4479 from unknownbrackets/perf 
Small optimizations (armjit) for imms
 2013-11-08 11:45:16 -08:00
Unknown W. Brackets 5d46a82f43 armjit: Use a MOV for add/or with 0. 
Might skip the ALU, so might be faster.
 2013-11-08 11:41:57 -08:00
Unknown W. Brackets b8e126e7ce armjit: Preserve imms in slt/sltu as possible. 2013-11-08 11:41:57 -08:00
Unknown W. Brackets 8393d4aaae armjit: Preserve immediates more in nor. 2013-11-08 11:41:56 -08:00
Unknown W. Brackets d7e42b26a3 armjit: Avoid flushing imm on add t0, imm, imm. 2013-11-08 11:41:56 -08:00
Unknown W. Brackets a435c9dd13 armjit: Optimize movz/movn with immediates. 2013-11-08 11:41:55 -08:00
Unknown W. Brackets 376918c408 armjit: Reverse add t0, N, t1 to preserve imm. 2013-11-08 11:41:55 -08:00
Unknown W. Brackets 02dd250354 armjit: Optimize out a few immediate logic cases. 2013-11-08 11:39:24 -08:00