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67 Commits

Author SHA1 Message Date
Unknown W. Brackets 5e01119d60 Update the debugger on a break instruction. 
Before it would still show "Stop" even though it was paused.
 2014-01-26 11:57:40 -08:00
Henrik Rydgard 2140892074 Initial preparations for ability to replace game functions with custom implementations. 
Also auto-saves hashmap additions and reapplies the hashmap on function
rename so that if you rename a function that exists in several copies
they will all be labelled.

Note that actual function replacement is not activated yet.
 2013-12-17 12:27:20 +01:00
Henrik Rydgard d394282bc6 Don't crash trying to clear the icache in interpreter mode 2013-12-10 20:34:07 +01:00
Henrik Rydgard 70d492e7e2 "cache" instruction: Implement icache invalidation. 
Fixes broken math in Tony Hawk so it must be doing self modifying code. Nasty.
 2013-12-10 13:15:28 +01:00
Henrik Rydgard a2e0a4d9bf x86 jit: Optimize ES, NS (is-nan-or-inf) conditions in vcmp 2013-11-12 14:07:48 +01:00
Sacha 61e6054920 Revert change to WSBH as we don't have a swap16 that takes/returns u32. 2013-11-06 01:38:02 +10:00
Sacha a5011e3ff0 Improve swap usage in MIPS. ARMv6 can use REV/REV16. Intepreter can use existing swap functions. 2013-11-06 01:20:35 +10:00
Unknown W. Brackets 732ae13ebb Fast path CallSyscall where possible. 
It seems we're spending a decent amount of time there, which isn't
entirely unexpected.  We can eliminate some things easily.
 2013-11-04 07:59:37 -08:00
Unknown W. Brackets baa82e0a9d Keep syscalls the same in the interpreter. 
Rather than having different bugs.
 2013-11-04 07:59:36 -08:00
Henrik Rydgård 0e54e24b24 Revert "Use swap code from native instead. Remove all other versions of it." 
Broke movie playback.

This reverts commit 9fcb08a326.

Conflicts:
	native
 2013-10-28 17:24:03 +01:00
Sacha 9fcb08a326 Use swap code from native instead. Remove all other versions of it. 2013-10-28 03:07:32 +10:00
Unknown W. Brackets 2e8ef3027f Write the retaddr to rd, not always ra, in jalr. 
Thanks go entirely to @Kingcom for pointing this out.

Don't know of any games not using RA as the rd.
 2013-10-17 07:39:33 -07:00
Unknown W. Brackets 7b71dc54dd Don't say nan is equal to anything. 
I guess we were passing this because of fastmath?  Fixes interpreter
cpu/fpu/fpu test on Windows anyway.
 2013-09-13 21:28:59 -07:00
Unknown W. Brackets 455431ba13 Integer round inf/nan to INT_MAX/INT_MIN. 
Instead of 0x80000000 (the default "invalid" value.)
Improves the fpu test.
 2013-09-13 21:27:31 -07:00
Henrik Rydgard 8c88dff5a4 More log categories, use them (and existing ones). Improve log config. 2013-09-07 22:02:55 +02:00
The Dax a35a407207 Add two new instructions to the MIPS interpreter for logging. vertex.pbp demo seems to use one of them. 2013-08-25 16:28:19 -04:00
Unknown W. Brackets 109ad17ac6 Use a typesafe struct for opcodes. 
Also, correctly read delayslots using Read_Instruction on ARM.
 2013-08-24 15:36:24 -07:00
Unknown W. Brackets b37f09cedf Make MIPSInfo a struct for typesafety. 
Found a bug in ReadsFromReg().
 2013-08-24 13:22:10 -07:00
Unknown W. Brackets 1ed8edb0d3 Avoid some dangerous hex constant widths. 2013-08-22 23:23:48 -07:00
Unknown W. Brackets 3f49101868 Clean up the COP1 MIPS tables, and reporting. 2013-08-11 19:35:39 -07:00
Unknown W. Brackets 7e92b17dd4 Cleanup some COP2/VFPU2 table flags. 2013-08-11 19:13:41 -07:00
Unknown W. Brackets d08f2bc3fb Fix some formatting in the MIPS table. 
And also a couple cases of manually specifying RS.
 2013-08-11 17:12:54 -07:00
The Dax 0ce45848b5 These funcs are already defined in math_util.h, so why are they redefined in this file? In any case, it seems to break 2010/2012 compilation to have those in there.. 2013-07-29 19:31:31 -04:00
Unknown W. Brackets abe3d95877 Revert "Remove hack for BREAK in Sol Trigger" 
This reverts commit 3d2c3c7227.

This wasn't a hack dedicated to Sol Trigger.  It helps other games, and
keeping it is just like allowing games to continue on bad memory address
reads.
 2013-06-26 07:56:36 -07:00
raven02 3d2c3c7227 Remove hack for BREAK in Sol Trigger 2013-06-26 19:27:36 +08:00
Henrik Rydgard e809e39681 Mips interpreter: Use unions instead of ugly casts. Strict-aliasing builds now work, but needs more testing so I don't enable it yet. Also some aliasing fixes for TransformPipeline. 2013-06-11 21:44:37 +02:00
Henrik Rydgard c5c3189436 Fix some framebuffer-related crash bugs. Ignore cache instruction 'FILL'. 2013-04-27 20:06:31 +02:00
Henrik Rydgard 06679fcce6 Switch to homemade isinf/isnan implementations. 2013-04-13 21:51:38 +02:00
raven02 39c3cf8744 Ignore MIPS break error 2013-04-09 16:13:24 +08:00
niepodam 94c2f0cd9d Fix build with gcc 4.8.0 2013-04-04 19:16:15 +02:00
Henrik Rydgard 5293c152c6 Untested support for Android-x86. No idea if this actually works. 2013-03-21 20:52:33 +01:00
Henrik Rydgard 062c975b46 Ignore cache function 24. 2013-03-04 23:51:19 +01:00
Unknown W. Brackets ac1209204c Add some reporting for CPU related stuff. 2013-03-04 00:01:41 -08:00
Henrik Rydgard 516ca8a0c4 Merge branch 'master' into armjit-fpu 
Conflicts:
	Core/MIPS/ARM/ArmJit.h
	Core/MIPS/x86/CompVFPU.cpp
	GPU/GLES/Framebuffer.cpp
 2013-02-28 23:56:28 +01:00
Unknown W. Brackets 2164a7fdf9 Keep track of whether we're in the runloop or not. 2013-02-23 13:01:00 -08:00
Unknown W. Brackets 08923c092b Implement ins and ext in the x86 jit. 2013-02-21 01:25:01 -08:00
Unknown W. Brackets 2bdc9dc491 Reset llBit on thread switch. 
Never actually seen ll used, though... but this way it should
work as advertized, as long as a syscall doesn't happen in between...
 2013-02-20 12:09:13 -08:00
Unknown W. Brackets 3a365fef64 Protect against some writes to $0. 2013-02-20 12:09:12 -08:00
Henrik Rydgard 44e4ba8772 Merge branch 'master' into armjit-fpu 2013-02-15 21:42:44 +01:00
Unknown W. Brackets abe390e6f3 Add some checks for fpu/vfpu writing to $0. 2013-02-14 00:27:09 -08:00
Henrik Rydgard b0c160fa93 Fix armjit fpu load / store 2013-02-13 21:07:06 +01:00
Unknown W. Brackets 19cc652a37 Correct NaN handling in fpu comparisons. 2013-02-13 01:54:07 -08:00
Unknown W. Brackets 3cab6986c5 Jit the FPU comparisons on x86. 
Probably not too fast.  Also, NaN handling seems wrong?
 2013-02-13 00:55:10 -08:00
Unknown W. Brackets 44b5adeaac Properly jit the break instruction. 
Otherwise, it just keeps on going past it.
We never want to hit this anyway, but it's good to know if we do.
 2013-02-01 00:49:14 -08:00
Henrik Rydgard 29f1ae5f70 add skeleton implementation of "cache" instruction 2013-01-22 22:03:41 +01:00
Unknown W. Brackets c324983340 Make the jit support bltzal and friends. 
Fixes problems with jit in games.  Android changes completely untested.
 2013-01-22 08:04:01 -08:00
Unknown W. Brackets d99d060c2e Decrement downcount in skipped likely slots. 
Pretty sure this is right, it eats up a cycle as a nop.

Also some funny indentation.
 2013-01-21 19:00:09 -08:00
Henrik Rydgard 8915677241 More progress but it weirds out... 2013-01-08 21:24:42 +01:00
Arthur Blot decbf9da81 Fixed interpreter 2013-01-03 17:01:12 +01:00
Arthur Blot be91ad2f9c Fixed $zr being non-zero after loading instruction 2013-01-03 16:14:45 +01:00