 Henrik Rydgard
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5a02ea9ff4
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Fix cache instruction on ARM
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2013-12-10 13:26:32 +01:00 |
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Unknown W. Brackets
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98fb2e0402
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armjit: Refer to R11 as MEMBASEREG for clarity.
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2013-11-14 23:37:48 -08:00 |
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Unknown W. Brackets
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67eaa2fd1c
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armjit: Optimize immediate load/stores in a row.
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2013-11-10 16:32:48 -08:00 |
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Unknown W. Brackets
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7e46ee0b0f
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armjit: Replace MOVI2R with using the regcache.
So that it can optimize the value with existing imms.
Not actually optimizing yet.
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2013-11-10 15:50:45 -08:00 |
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Unknown W. Brackets
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455a7e090d
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Compile the cache instruction to nothing.
Was showing up in a few profiles, does nothing currently.
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2013-11-10 14:38:10 -08:00 |
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Unknown W. Brackets
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b2c2a87511
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Fix omitted CC_AL reset, fixes #4498.
Was breaking non-fastmem lwl/lwr/etc.
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2013-11-10 09:24:40 -08:00 |
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Unknown W. Brackets
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3aa8706ae7
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armjit: Optimize lwl/lwr against an imm address.
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2013-11-09 08:43:48 -08:00 |
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Unknown W. Brackets
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4026944b02
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armjit: Handle lwl/lwr (not pretty, though.)
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2013-11-09 08:42:30 -08:00 |
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Unknown W. Brackets
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cb3bb73148
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armjit: Improve GPR typesafety.
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2013-11-09 08:24:15 -08:00 |
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Henrik Rydgard
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502f772856
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Add experimental mode to cache pointers in the arm jit.
Turned off for now as it needs more work but seems quite promising already.
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2013-11-09 17:15:30 +01:00 |
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Henrik Rydgard
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309f904c0c
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Extract JitState into its own header (arm/x86)
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2013-11-08 18:51:52 +01:00 |
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Henrik Rydgard
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32c95af820
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ARM: Some zero-register fixes
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2013-11-07 15:29:13 +01:00 |
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Unknown W. Brackets
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157b682344
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Always use fastmem for sw/lw on SP.
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2013-09-07 22:44:18 -07:00 |
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Unknown W. Brackets
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97aa1a631e
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Improve typesafety in the x86 regalloc.
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2013-08-24 19:41:10 -07:00 |
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Unknown W. Brackets
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109ad17ac6
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Use a typesafe struct for opcodes.
Also, correctly read delayslots using Read_Instruction on ARM.
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2013-08-24 15:36:24 -07:00 |
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Unknown W. Brackets
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1ed8edb0d3
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Avoid some dangerous hex constant widths.
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2013-08-22 23:23:48 -07:00 |
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Unknown W. Brackets
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796d2c10c6
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armjit: VRAM comes before RAM, fix slowmem check.
Can't think of anything else, hopefully fixes #1021.
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2013-03-18 08:08:40 -07:00 |
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Unknown W. Brackets
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b8eb526691
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armjit: improve slowmem, fix vram check.
Darn, copy/paste error.
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2013-03-16 20:31:51 -07:00 |
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Unknown W. Brackets
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6ef5f4c8dc
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armjit: Refactor slowmem path for reusing it.
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2013-03-16 14:37:35 -07:00 |
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Unknown W. Brackets
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45b0b1203f
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armjit: No, LDR/STR do not update flags.
Oops, had some other bug and thought this was the issue.
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2013-03-16 14:37:35 -07:00 |
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Unknown W. Brackets
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de3713fc50
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armjit: improve mem speed without fastmem.
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2013-03-16 14:37:35 -07:00 |
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Unknown W. Brackets
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8f3904d32d
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armjit: Speed up imm addresses in slowmem mode.
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2013-03-16 14:37:35 -07:00 |
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Sacha
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529803e429
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Sonic's ArmEmitter changes (cross-project merge from Dolphin)
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2013-03-14 12:47:29 +10:00 |
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Sacha
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8125d96ce1
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Small update for shifted load/stores. Still disabled.
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2013-03-07 01:04:41 +10:00 |
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Sacha
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a8b6fca61b
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Separate codepaths for shifted load/stores and normal load/stores. Fix dirty regs.
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2013-03-07 00:59:07 +10:00 |
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Sacha
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ae3b881a7f
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Use correct args for Operand2(..) through armjit. Fix STR(..).
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2013-03-07 00:59:07 +10:00 |
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Sacha
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268d16bd24
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Use correct args for STR(..) throughout armjit.
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2013-03-07 00:59:07 +10:00 |
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Sacha
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23fb88c5fe
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Enable optimisation codepath (left+right combines).
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2013-03-07 00:59:07 +10:00 |
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Henrik Rydgard
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9f327985fc
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armjit: disable lwl/lwr/swl/swr
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2013-03-05 23:09:26 +01:00 |
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Sacha
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5a134243a7
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Armjit: Fix lwl, lwr and enable again. Thanks Sonic.
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2013-03-06 03:28:28 +10:00 |
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Sacha
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7e67de3334
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Armjit: Implement lwl, lwr, swl, swr in ARM JIT. lwr is currently disabled as it isn't working.
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2013-03-06 02:11:36 +10:00 |
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Sacha
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9152d2f2bb
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Armjit: Optimise swl+swr and lwl+lwr cases that can be combined to a single sw or lw. Add shift flags to STR/LDR. Add EatInstruction to ArmJit.
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2013-03-06 02:11:36 +10:00 |
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Unknown W. Brackets
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ab05149dbf
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Add a few more CONDITIONAL_DISABLEs.
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2013-03-03 01:44:33 -08:00 |
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Henrik Rydgard
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516ca8a0c4
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Merge branch 'master' into armjit-fpu
Conflicts:
Core/MIPS/ARM/ArmJit.h
Core/MIPS/x86/CompVFPU.cpp
GPU/GLES/Framebuffer.cpp
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2013-02-28 23:56:28 +01:00 |
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Sacha
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8d4400fba1
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ARMJIT: Clean up for load/stores
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2013-02-27 22:17:38 +10:00 |
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Sacha
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ff14815fda
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ARMJIT: Combine to one instruction for load/stores.
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2013-02-27 19:45:01 +10:00 |
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Sacha
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2c59de95e9
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JIT the signed load/store variants too
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2013-02-27 18:05:45 +10:00 |
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Sacha
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fe8b80c12e
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ARM JIT: Add and simplify some half-word load/store instructions.
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2013-02-27 17:09:47 +10:00 |
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Henrik Rydgard
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b0c160fa93
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Fix armjit fpu load / store
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2013-02-13 21:07:06 +01:00 |
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Henrik Rydgard
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78923f5538
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Jit a little more (vfpu single load/store, transfer instructions)
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2013-02-10 12:14:55 +01:00 |
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Henrik Rydgard
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d8f4e27926
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Rename ARMABI_MOVI2R to MOVI2R
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2013-01-31 23:41:05 +01:00 |
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Henrik Rydgard
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aabc0aa9ef
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Quick implementation of LV.Q and SV.Q in x86/x64 JIT
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2013-01-25 19:50:30 +01:00 |
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Henrik Rydgard
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64f953c5e1
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8-byte align the ARM stack. Type some ideas.
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2013-01-12 12:26:44 +01:00 |
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Henrik Rydgard
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36eaabd917
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Some constant propagation. Comment out sltiu which causes problems aiming in puzbob (???)
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2013-01-11 23:42:58 +01:00 |
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Henrik Rydgard
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37be2600be
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Shave some more instructions
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2013-01-11 18:50:05 +01:00 |
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Henrik Rydgard
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bc9c3db303
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Armjit: Add option for fastmem. Small optimization.
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2013-01-11 17:25:54 +01:00 |
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Henrik Rydgard
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9b791b9953
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More ARMJIT optimization
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2013-01-11 15:22:31 +01:00 |
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Henrik Rydgard
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8cd5ae933f
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sw/lw
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2013-01-10 12:14:23 +01:00 |
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Henrik Rydgard
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a2ff416534
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Rename files. Rewrite ArmRegCache from scratch.
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2013-01-07 22:33:09 +01:00 |
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