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Author SHA1 Message Date
Henrik Rydgard 497915141b Revert to normal for loop in the index generator, the < 3 case gets taken care of properly. Just existing caused some issues. 2013-11-09 19:33:40 +01:00
Henrik Rydgard 0a844ce98d Delete functions for vsge and vslt, these have been rolled into VecDo3 2013-11-09 19:29:52 +01:00
Henrik Rydgård ed6190fd24 Merge pull request #4485 from sum2012/patch-1 
Fix Colin Mcrae Dirt 2 Crash
 2013-11-09 10:25:11 -08:00
sum2012 886fcdd0b1 Fix Colin Mcrae Dirt 2 Crash 
#4482
 2013-11-10 02:23:22 +08:00
Henrik Rydgard 63334698e1 Add temporary setting to disable the vertex decoder jit while we debug it 2013-11-09 18:16:26 +01:00
Henrik Rydgård 6bc2df051e Merge pull request #4484 from unknownbrackets/armjit-ops 
Implement some more ops in armjit (divu, lwl, lwr, msub, msubu)
 2013-11-09 08:58:32 -08:00
Unknown W. Brackets a3a061a69f armjit: Optimize a division by a power of two. 
These really happen.
 2013-11-09 08:43:53 -08:00
Unknown W. Brackets 1776c85882 armjit: Implement a software divide for divu. 
It's not actually that much code.
 2013-11-09 08:43:52 -08:00
Unknown W. Brackets b2a240d105 armjit: Implement msub/msubu. 2013-11-09 08:43:52 -08:00
Unknown W. Brackets 3aa8706ae7 armjit: Optimize lwl/lwr against an imm address. 2013-11-09 08:43:48 -08:00
Unknown W. Brackets 83fe874dcc armjit: Use multiple BICs in ANDI2R if possible. 
Rather than a temporary.
 2013-11-09 08:42:31 -08:00
Unknown W. Brackets 4026944b02 armjit: Handle lwl/lwr (not pretty, though.) 2013-11-09 08:42:30 -08:00
Henrik Rydgård e90f7f360d Merge pull request #4480 from unknownbrackets/perf 
Flush regs using STMIA if possible, plus imm adjustments (armjit)
 2013-11-09 08:41:25 -08:00
Henrik Rydgard 06ce01ea04 Remove erroneous comment. 2013-11-09 17:34:52 +01:00
Unknown W. Brackets 54168b173e armjit: Clean up some magic numbers. 2013-11-09 08:25:08 -08:00
Unknown W. Brackets 6038d96b46 armjit: Flush regs using STMIA where possible. 2013-11-09 08:25:07 -08:00
Unknown W. Brackets e686ff59bf armjit: Allocate regs in preferred slots. 
This may allow better flushing.  Not sure if these are the best regs,
but if they aren't it shouldn't really hurt.
 2013-11-09 08:25:07 -08:00
Unknown W. Brackets cb3bb73148 armjit: Improve GPR typesafety. 2013-11-09 08:24:15 -08:00
Unknown W. Brackets 945b8bf5c5 armjit: optimize reverse subtract, avoid temp imms. 
If we have a non-op2 imm, get rid of it asap.  If we have a op2 friendly
imm, keep it.
 2013-11-09 08:18:43 -08:00
Unknown W. Brackets 415f22ecac armjit: Preserve imms on min/max as well. 2013-11-09 08:18:43 -08:00
Henrik Rydgard 502f772856 Add experimental mode to cache pointers in the arm jit. 
Turned off for now as it needs more work but seems quite promising already.
 2013-11-09 17:15:30 +01:00
Henrik Rydgard 58c39a38ee ARM regcache: Add mechanism to keep registers converted to pointers around 2013-11-09 16:57:29 +01:00
Henrik Rydgard 5ad04a23f4 x86 jit: Rename BindToRegister to MapReg 2013-11-09 15:23:31 +01:00
Henrik Rydgard d26692ef92 Fix bug from a couple of commits ago in ARMJit 2013-11-09 15:22:39 +01:00
Henrik Rydgard 316d23d4cc Optimize mfv/mtv/mfc1/mtc1 on x86 too 2013-11-09 14:06:45 +01:00
Henrik Rydgard 04451623b9 This variant didn't seem to make much difference either (see prev commit) 2013-11-09 13:06:10 +01:00
Henrik Rydgard 15bc5a8db7 Add small ARM perf experiment. Did not help on ARMv7 so turned it off. 
xsacha might want to try it on ARMv6.
 2013-11-09 12:57:07 +01:00
Henrik Rydgard 2fe898cda8 Add comment with link to important github thread about sceSas threading 2013-11-09 02:05:28 +01:00
Henrik Rydgård d04415ac5d Merge pull request #4479 from unknownbrackets/perf 
Small optimizations (armjit) for imms
 2013-11-08 11:45:16 -08:00
Unknown W. Brackets 5d46a82f43 armjit: Use a MOV for add/or with 0. 
Might skip the ALU, so might be faster.
 2013-11-08 11:41:57 -08:00
Unknown W. Brackets b8e126e7ce armjit: Preserve imms in slt/sltu as possible. 2013-11-08 11:41:57 -08:00
Unknown W. Brackets 8393d4aaae armjit: Preserve immediates more in nor. 2013-11-08 11:41:56 -08:00
Unknown W. Brackets d7e42b26a3 armjit: Avoid flushing imm on add t0, imm, imm. 2013-11-08 11:41:56 -08:00
Unknown W. Brackets a435c9dd13 armjit: Optimize movz/movn with immediates. 2013-11-08 11:41:55 -08:00
Unknown W. Brackets 376918c408 armjit: Reverse add t0, N, t1 to preserve imm. 2013-11-08 11:41:55 -08:00
Unknown W. Brackets 02dd250354 armjit: Optimize out a few immediate logic cases. 2013-11-08 11:39:24 -08:00
Unknown W. Brackets 385f9a457e Use GetPointerUnchecked in how, pre-checked areas. 2013-11-08 11:39:24 -08:00
Henrik Rydgard 0e542b6ecc vtxdec: small omission 2013-11-08 20:38:49 +01:00
Henrik Rydgard 4daebe9b0f When logging PRIM commands, print the prim number 2013-11-08 20:36:42 +01:00
Henrik Rydgård 4df08e49e9 Merge pull request #4478 from Kingcom/Debugger 
Reset cycle counter when stepping out
 2013-11-08 11:04:49 -08:00
Henrik Rydgard 22d6b36005 Vertexdecoder "double": fix for x86 and very minor optimization for arm. 2013-11-08 20:03:28 +01:00
Henrik Rydgard 58db79672f Fix vmtvc on ARM, fixing issues with our prefix check. Add some logging. 
Also improve vcmp on ARM.
 2013-11-08 19:59:11 +01:00
Henrik Rydgard a028f07951 Turn down some logging. 2013-11-08 18:52:07 +01:00
Henrik Rydgard 309f904c0c Extract JitState into its own header (arm/x86) 2013-11-08 18:51:52 +01:00
Henrik Rydgard 6b45c321b6 vtxdecjit: turn off excessive logging 2013-11-08 18:49:17 +01:00
Kingcom ee553afebc Reset cycle counter when stepping out 2013-11-08 17:41:50 +01:00
Henrik Rydgard f57f8170d3 ARMjit: Optimize mfv, mtv 2013-11-08 12:43:48 +01:00
Henrik Rydgard dff0c431aa ARMjit: Optimize mfc1, mtc1 2013-11-08 12:43:48 +01:00
Henrik Rydgard 5a95e267fb Add an optimization to discard registers at the end of functions when possible. 
Works in some games but crashes many so hiding it for now. Do not add UI.
 2013-11-08 12:43:48 +01:00
Henrik Rydgard 9a51d25279 Minor optimization in IndexGenerator::AddStrip. 2013-11-08 12:43:47 +01:00