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Code Issues Packages Projects Releases Wiki Activity
39,166 Commits 98 Branches 131 Tags
ca94de8d4b1e53b7d596d31e7336ac5133a32a7c
Commit Graph
12833 Commits
Author SHA1 Message Date
Unknown W. Brackets 03f22beefd arm64jit: Implement Vec2Pack32To16. 2023-09-06 20:20:52 -07:00
Unknown W. Brackets 178bb8416b arm64jit: Implement FSpecial. 2023-09-06 20:08:36 -07:00
Unknown W. Brackets fad24e3b44 arm64jit: Implement FSign. 2023-09-06 19:53:49 -07:00
Unknown W. Brackets a1304f6ac8 arm64jit: Implement VFPU compare in IR. 2023-09-06 19:02:24 -07:00
Henrik Rydgård 61af237f98 Check v.on for whether to trigger v.playing, like before. 2023-09-06 15:46:07 +02:00
Henrik Rydgård 9f984af48c Merge pull request #18082 from hrydgard/retroachievements-logspam-fix 
Retroachievements logspam fix, edge case fixes
 2023-09-06 15:03:35 +02:00
Henrik Rydgård 8b32a1e5e2 Remove the weird ChangedParams thing entirely and do the straightforward thing 2023-09-06 14:52:57 +02:00
Henrik Rydgård 9794d5377b Always reinitialize the VAG decoder on sceSasSetVoice, even if already playing. Fixes After Burner. 2023-09-06 11:25:19 +02:00
Henrik Rydgård 1ee4c63bba Logging: __sceCore isn't very interesting, log as verbose 2023-09-06 11:25:19 +02:00
Henrik Rydgård a84f08e55e Typo fix 
See #18080
 2023-09-06 11:21:41 +02:00
Henrik Rydgård ce82179321 Avoid checking for achievements for homebrew. Fix edge case. 2023-09-06 11:19:13 +02:00
Henrik Rydgård b61fa7053f RetroAchievements: Add parameter to SetGame for IdentifiedFileType, also add bool return to SaveSecret 2023-09-06 10:56:51 +02:00
Henrik Rydgård cd79d120d8 Don't log warnings on missing RA login secret. Also don't even check unless a username has been set. 2023-09-06 10:34:32 +02:00
Henrik Rydgård 1bfa566b3d Merge pull request #18081 from unknownbrackets/arm64jit-float 
arm64jit: Implement some float compares and conversions
 2023-09-06 10:11:56 +02:00
Henrik Rydgård f2512e0fdd Merge pull request #18080 from unknownbrackets/x86jit-minor 
x86jit: Correct jitbase range comparison
 2023-09-06 09:23:55 +02:00
Unknown W. Brackets 01ed48a3d0 arm64jit: Implement FCvtSW. 2023-09-06 00:09:26 -07:00
Unknown W. Brackets 89a9584c38 arm64jit: Implement FRound/similar. 2023-09-06 00:09:26 -07:00
Unknown W. Brackets 97d9a7f07f arm64jit: Implement FCmp. 2023-09-06 00:09:26 -07:00
Unknown W. Brackets c8f888fab0 arm64jit: Implement FMin/FMax. 2023-09-06 00:09:26 -07:00
Unknown W. Brackets 0fc337cdc1 x86jit: Correct jitbase range comparison. 2023-09-05 23:56:36 -07:00
Henrik Rydgård 6c3547d7ae Merge pull request #18073 from unknownbrackets/arm64jit-vec4 
arm64jit: Implement several other Vec4 IR ops
 2023-09-06 08:55:57 +02:00
Henrik Rydgård 95e86c73b8 SasAudio: Some cleanup and debug overlay improvements 
Shows "BAD" in the overlay if address out of range.

Which does happen in Afterburner, see issue #14010.
 2023-09-05 12:15:13 +02:00
Unknown W. Brackets 953d97b54a arm64jit: Implement Vec4Init. 2023-09-05 00:10:26 -07:00
Unknown W. Brackets 11f92b4684 arm64jit: Implement Vec4Dot. 2023-09-05 00:10:26 -07:00
Unknown W. Brackets 81aeb04788 arm64jit: Implement Vec4Blend. 2023-09-05 00:10:26 -07:00
Unknown W. Brackets 85387b44a1 arm64jit: Implement Vec4Scale. 2023-09-05 00:10:26 -07:00
Unknown W. Brackets 3f29b4c713 Merge pull request #18068 from unknownbrackets/arm64jit-shuffle 
arm64jit: Implement shuffle optimizer
 2023-09-05 00:10:08 -07:00
Henrik Rydgård 37fc621d8a Merge pull request #18071 from unknownbrackets/arm64jit-muldiv 
arm64jit: Implement IR multiplies and divides
 2023-09-05 09:07:02 +02:00
Unknown W. Brackets d8231ecb17 arm64jit: Implement divide in IR. 2023-09-04 23:38:55 -07:00
Unknown W. Brackets c272284043 arm64jit: Implement multiplies in IR. 2023-09-04 23:38:55 -07:00
Unknown W. Brackets 17ffc9c261 arm64jit: Special case some shuffles. 
To avoid 4 instruction shuffles.
 2023-09-04 23:37:40 -07:00
Henrik Rydgård 67cb466ee1 Allow using a file browser to choose UMDs during disc change. 2023-09-04 21:43:10 +02:00
Unknown W. Brackets 885ae5c805 arm64jit: Implement shuffle optimizer. 2023-09-04 12:27:39 -07:00
Henrik Rydgård 9690a71a14 Merge pull request #18061 from unknownbrackets/arm64-ir-jit 
arm64jit: Implement most ALU and load/store in IR jit
 2023-09-04 10:02:24 +02:00
Unknown W. Brackets 494aab62fc Merge pull request #18063 from unknownbrackets/arm64-ir-float 
arm64jit: Add some initial float and vec4 ops
 2023-09-04 00:08:08 -07:00
Unknown W. Brackets 5134b7eedb Merge pull request #18064 from unknownbrackets/arm64-ir-exit 
arm64jit: Implement exits and a few system ops
 2023-09-04 00:07:13 -07:00
Unknown W. Brackets 85b80bc9e5 arm64jit: Implement load/store in IR. 2023-09-04 00:04:36 -07:00
Unknown W. Brackets ccee8e41ee arm64jit: Implement exits. 2023-09-03 21:16:08 -07:00
Unknown W. Brackets e02426cbbf arm64jit: Implement some system ops. 2023-09-03 21:16:08 -07:00
Unknown W. Brackets 0933381b9e arm64jit: Add some simple vec4 ops. 2023-09-03 21:14:58 -07:00
Unknown W. Brackets 87b9633258 arm64jit: Add some simple float ops. 2023-09-03 21:14:58 -07:00
Unknown W. Brackets 1042737c21 irjit: Correct metadata on Vec2 packing ops. 2023-09-03 21:13:11 -07:00
Unknown W. Brackets c44f0e1fca arm64jit: Implement most ALU in IR jit. 2023-09-03 15:30:55 -07:00
Henrik Rydgård 2f300c2023 Merge pull request #18060 from unknownbrackets/x86-jitbase 
x86jit: Bake emuhack mask into jitbase
 2023-09-03 22:53:23 +02:00
Henrik Rydgård daa0586641 Merge pull request #18059 from unknownbrackets/arm64-ir-jit 
arm64jit: Add initial base for IR jit
 2023-09-03 22:33:24 +02:00
Unknown W. Brackets 9439a43323 riscv: Correct an overlap case, fix assert. 2023-09-03 13:29:57 -07:00
Unknown W. Brackets 0452b8b57a riscv: Account for emuhack in JITBASEREG. 2023-09-03 13:29:05 -07:00
Unknown W. Brackets 1d152a1486 x86jit: Bake emuhack mask into jitbase. 2023-09-03 12:49:36 -07:00
Henrik Rydgård 4694a11b9f Merge pull request #18053 from unknownbrackets/x86-jit-debug 
x86jit: Handle breakpoints
 2023-09-03 21:45:48 +02:00
Unknown W. Brackets 60bcc5b083 x86jit: Handle breakpoints. 
Otherwise, we don't actually break until later, which isn't great.
Could be more optimal, "rewinding" regcache state.
 2023-09-03 12:28:11 -07:00