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39,166 Commits 78 Branches 131 Tags
ca94de8d4b1e53b7d596d31e7336ac5133a32a7c
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8 Commits
Author SHA1 Message Date
Unknown W. Brackets 2a24c99441 arm64jit: Correct FlushBeforeCall pairing. 
Oops, some silly mistakes here.
 2023-10-14 20:54:40 -07:00
Unknown W. Brackets 4380bf9787 arm64jit: Optimize transfers to vec4 better. 2023-09-30 15:44:53 -07:00
Unknown W. Brackets cb835295c8 arm64jit: Implement reg lane transfers. 2023-09-30 15:44:41 -07:00
Unknown W. Brackets 88b6442527 irjit: Add facility for native reg transfer. 2023-09-24 16:28:29 -07:00
Unknown W. Brackets decccf199a x86jit: Flush floats together if possible. 2023-09-24 08:01:05 -07:00
Unknown W. Brackets 03f22beefd arm64jit: Implement Vec2Pack32To16. 2023-09-06 20:20:52 -07:00
Unknown W. Brackets c44f0e1fca arm64jit: Implement most ALU in IR jit. 2023-09-03 15:30:55 -07:00
Unknown W. Brackets 1b756ff8c1 arm64jit: Add initial base for IR jit. 
This works, but very slowly at this point.
 2023-09-03 12:14:28 -07:00