Commit Graph
26 Commits
Author SHA1 Message Date
libretroadmin f1208a7a5a Make threading lock-free
The core and the headless tools no longer use mutexes, condition variables,
spinlocks, std::atomic, std::thread or volatile flags. Threads hand off through
libretro-common's retro_atomic and rthreads plus a few small pieces on top of
them in Common/Thread: Thread, MpscQueue, EventCounter, ParkingLot waits and
ReaderGate. Every wait blocks until it's woken; nothing polls on a timer.

State that only one thread touches just loses its lock. The PSP filesystem,
sceIo and the savedata dialog now belong to the emulation thread: async reads
and writes run when they're queued and complete later in emulated time, and
the IO and savedata threads are gone. The friend finder only talks to the
adhoc server and hands what it gets to the emulation thread. GPU init always
runs on the thread that starts the game.

The Vulkan render and compile queues, pipeline and render pass caches, delete
list and SPIR-V cache, the GL render queue, the software renderer's jit caches,
the file loader caches, the web debugger, UPnP, input, savestates, logging and
the GE debugger all hand off through queues and atomics. The IR jit's spinning
profiler thread goes.

A CPU thread with nothing to run now sleeps until work is queued instead of
spinning. Headless with --debugger waits for a client while stopped, and ends
the run once every client that connected has left. Web server shutdown keeps
servicing the CPU queue until the server has finished.
2026-10-09 04:56:16 +02:00
Henrik Rydgård f046857d2b Delete remains of support for the MIPS architecture as host 2026-02-17 10:20:51 +01:00
Lin Runze 5b406f00fd loongarch: Initial VertexJIT support and bug fix 2025-07-17 00:33:56 +08:00
Henrik Rydgård d5bfc1b5eb Finish up this cleanup (move _M_SSE compat define out of Common.h) 2024-12-19 16:23:20 +01:00
Unknown W. Brackets 89c18d8077 riscv: Cleanup missing Poison, Crash. 2023-02-12 12:10:29 -08:00
Henrik Rydgård cd92151de7 Add ARM64_NEON compile arch flag
This allows doing ARM64 builds without NEON support, and allows simplifying some checks.
2022-06-25 07:29:20 +02:00
Unknown W. Brackets 99d7703d33 samplerjit: Precalculate DXT1/3/5 offsets.
This improves WALL-E by 8% overall.
2022-02-05 13:04:17 -08:00
Unknown W. Brackets 2479d52202 Global: Reduce includes of common headers.
In many places, string, map, or Common.h were included but not needed.
2022-01-30 16:35:33 -08:00
Unknown W. Brackets eb70a90347 samplerjit: Avoid frac uv transfer to gen regs.
It should just stay in vec, this is more convenient anyway.
2022-01-28 23:50:54 -08:00
Unknown W. Brackets 6ec819878a samplerjit: Reduce prolog/epilog spill.
Track reg usage so we only push/pop what we need.
2022-01-19 00:03:59 -08:00
Unknown W. Brackets 357e2e9d68 softjit: Simplify constant writes. 2022-01-19 00:03:59 -08:00
Unknown W. Brackets c2985bca31 softjit: Centralize some common funcs from sampler.
No need to duplicate this code.
2022-01-19 00:03:59 -08:00
Unknown W. Brackets ac2b96cec0 softjit: Switch to constant pool.
This is simpler without RIP access checks, and tends to be fast.
2022-01-17 19:50:37 -08:00
Unknown W. Brackets edb79d968f softgpu: Cache CLUT params in sampler state.
And now there's no more gstate for pixel drawing or sampling.  Just a
little left in rasterization.
2022-01-15 18:09:09 -08:00
Unknown W. Brackets f1ce2e7715 softgpu: Cache minz/maxz in draw pixel state. 2022-01-15 13:03:10 -08:00
Unknown W. Brackets 22f770c828 samplerjit: Use VPGATHERDD for simple CLUT4 loads.
Planning to expand this to more paths.
2022-01-02 17:19:17 -08:00
Unknown W. Brackets 6aec68aa5c samplerjit: Correct wrong bufw at mip levels.
Oops, was always using the base bufw.
2022-01-01 16:40:02 -08:00
Unknown W. Brackets cdf14c8579 samplerjit: Calculate mip level U/V/offsets.
Not actually doing the sampling for the second mip level in the single jit
pass yet, but close.
2021-12-28 14:12:58 -08:00
Unknown W. Brackets a84accf713 samplerjit: Move S/T calculation into jit.
Gives a pretty decent 5-10% improvement in many places.
2021-12-28 09:58:23 -08:00
Unknown W. Brackets b00a66e34c samplerjit: Pass u/v coords as vector. 2021-12-27 11:37:32 -08:00
Unknown W. Brackets 823c4adb15 softgpu: Keep arguments in vectors for sampling. 2021-12-04 15:45:06 -08:00
Unknown W. Brackets d7c25b3e7c samplerjit: Refactor nearest using reg cache. 2021-12-04 13:04:53 -08:00
Unknown W. Brackets 99c213f244 softjit: Centralize argument register allocation. 2021-11-28 15:53:24 -08:00
Unknown W. Brackets 9653c33d9c softjit: Fix PixelFuncID arg on non-Windows x64.
Oops, this is of course not put on the stack, it's in R8.
2021-11-28 08:54:36 -08:00
Unknown W. Brackets 96a7554053 sofjit: Move common types to reg cache header.
This makes it easier to use vectors elsewhere.
2021-11-28 08:03:15 -08:00
Unknown W. Brackets 3d5bced296 softjit: Rename reg cache so it can be reused.
Intentionally just the name changes in this commit.
2021-11-28 08:03:15 -08:00