6 Commits

Include renames

Author	SHA1	Message	Date
Unknown W. Brackets	4e17c59cc2	riscv: Implement simple vec4 ops via floats.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	bb6fdd0246	riscv: Add floating point load/stores.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	94be343591	riscv: Try to keep regs normalized, track. ... Since we can't address the lower 32-bits only in compares, this can help us avoid renormalizing before a compare.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	165169eb31	riscv: Implement load and store ops.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	c2da7d18bb	riscv: Stub out more IR compilation categories.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	bf7a6eb2cd	riscv: Add jit for some initial instructions.	2023-07-23 18:01:00 -07:00