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24,508 Commits 86 Branches 131 Tags
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2023 Commits
Author SHA1 Message Date
Unknown W. Brackets b114656321 Debugger: Allow conditions on threadID/moduleID. 
And now step over/out/into can tie to the correct thread.
 2018-06-08 06:59:18 -07:00
Unknown W. Brackets b2cc4a0965 Debugger: Add memory breakpoint management. 2018-06-08 06:59:18 -07:00
Unknown W. Brackets 22940f0393 Debugger: Avoid asserts in disassembly. 2018-06-08 06:59:18 -07:00
Unknown W. Brackets 98cddad73a Debugger: Minor cleanup in MIPSDebugInterface. 2018-06-08 06:59:16 -07:00
Unknown W. Brackets 4c3fe47372 jit: Remove unused breakpoint code. 2018-06-06 17:31:56 -07:00
Unknown W. Brackets 5510a69d41 armjit: Enable breakpoints. 2018-06-06 17:31:56 -07:00
Unknown W. Brackets eb4b59b530 arm64jit: Enable breakpoints. 
Memory breakpoints not yet really tested.
 2018-06-06 17:31:56 -07:00
Henrik Rydgård f9cfb05895 Merge pull request #10987 from unknownbrackets/debugger-core 
Improve debugger threadsafety and consistency
 2018-06-06 21:10:14 +02:00
Unknown W. Brackets e21753bc93 Debugger: Add assembler to build. 2018-06-06 05:59:24 -07:00
Unknown W. Brackets 0f84c2e995 Debugger: Consistently handle invalid addresses. 2018-06-06 05:58:49 -07:00
Henrik Rydgård a3ed87bca5 Some comment fixes and cleanup. 
Not much point warning for those MIPS instructions - if games use them,
they use them carefully because games can't catch that exception anyway.
 2018-04-12 12:00:19 +02:00
Henrik Rydgård b4721fbc44 Temporary workaround for another IR interpreter crash. See #10897 2018-04-11 11:55:12 +02:00
Henrik Rydgård 3322adbc22 IR Interpreter: Add some missing instruction metadata. May help part of #10897 2018-04-11 11:16:41 +02:00
Unknown W. Brackets da0173f40c Module: Fix function hashing typo. 
May help #10895.
 2018-04-09 19:12:23 -07:00
Unknown W. Brackets 4861cadb79 arm64jit: Fix reg size in jr delay slot path. 
Can't use the 64-bit reg.
 2018-04-04 06:58:12 -07:00
Unknown W. Brackets ab809bd19e jit: Apply hasSetRounding at compile time. 
Otherwise, the block will be executed with the wrong rounding mode the
first time rounding is set.  This could be important if it was set for a
single operation.

This is only a problem the first time it's set.
 2018-04-01 10:36:16 -07:00
Unknown W. Brackets 09e307b097 arm64jit: Update rounding mode on thread switch. 
Since fcr31 is per-thread, we must update jit state when it changes.
This also fixes the rounding mode on load state and jit/interp switch.
 2018-04-01 10:12:32 -07:00
Unknown W. Brackets 7d3fac2b4b arm64jit: Fix a case of R() on unmapped. 
But this probably means a game crash anyway...

Attempting to fix #10843.
 2018-03-31 22:34:05 -07:00
Unknown W. Brackets 4fbb68d505 arm64jit: Update some comments. 2018-03-31 21:03:23 -07:00
aliaspider 0af6d573bb remove all usage of __LIBRETRO__ 2018-03-24 12:45:20 +01:00
Henrik Rydgård f76e5e70a7 Enable FlushInstructionCache on UWP, it's been allowed finally. 
Minor warning fixes, UWP buildfix

Retarget UWP project to latest SDK.
 2018-03-20 20:30:33 +01:00
Unknown W. Brackets 892c439fcf Module: Clarify insertSymbols usage. 2018-03-17 13:58:56 -07:00
Unknown W. Brackets f14f2efa79 Module: Hash functions only once during loading. 
This fixes the loading speed regression from #10501.
 2018-03-17 13:36:37 -07:00
Henrik Rydgård 813c376aed Tiny change to work around internal compiler error (!) in 32-bit builds with latest MSVC update 2018-02-11 13:39:04 +01:00
Henrik Rydgård 34f79904fd IR: This optimization is safe when all three regs are consecutive, so avoid disabling it unnecessarily. 2018-01-10 09:19:27 +01:00
Henrik Rydgård fb0e81484b Minor cleanup 2018-01-10 09:19:27 +01:00
Henrik Rydgård 4a32ec3102 Merge pull request #10516 from unknownbrackets/irjit-lwr 
irjit: Optimize out more temps and lwl/lwr operations
 2018-01-10 09:11:10 +01:00
Unknown W. Brackets b6bb0159e3 irjit: Remove Comp_ITypeMemLR. 2018-01-09 18:06:25 -08:00
Unknown W. Brackets f01e06aefd irjit: Improve multiple lwr in a row. 2018-01-07 21:06:02 -08:00
Unknown W. Brackets fbeedd333b irjit: Swap moves when it may allow clobbering. 
Example:
addiu a0, a1, a2
mov s0, a0
addiu a0, a2, a3

By swapping the mov, we can eliminate it.

Only going one back because it's common and didn't want to track reads.
 2018-01-07 21:06:02 -08:00
Unknown W. Brackets d27e428659 irjit: Convert lwr and friends to easier code. 
This makes it easier to write a (working) jit backend from IR, since these
ops are always annoying to get right.
 2018-01-07 21:06:00 -08:00
Unknown W. Brackets b11f00cead irjit: Combine lwl/lwr and swl/swr, like before. 
Still want to inline the operation, because the backend shouldn't have to
redo it every time, and we want the temps cleaned up if possible.
 2018-01-07 21:05:58 -08:00
Unknown W. Brackets c6d690e9b8 irjit: Handle Left/Right ops in passes. 2018-01-07 21:05:57 -08:00
Unknown W. Brackets 6dda053365 irjit: Add dedicated ops for lwl/swl and friends. 
Temporarily removes optimizations.
 2018-01-07 21:05:57 -08:00
Unknown W. Brackets cd3f4881a5 irjit: Optimize out temp lhs copies. 
Common example:
li v0, 1
beq s2, v0, somewhere
li v0, 2

Which was copying s2 before.  This pattern generally doesn't happen in
MIPS code, though, so really only catches that (very common) case.
 2018-01-07 12:11:16 -08:00
Unknown W. Brackets 97674b80bd irjit: Skip preloading blocks with jump to 0. 
These will be changed before executing anyway.
 2018-01-06 17:23:53 -08:00
Unknown W. Brackets cc8e9a93c3 irjit: For debug, return the best block at addr. 
Invalidation may result in multiple matching blocks, prefer any that is
currently valid.
 2018-01-06 17:08:54 -08:00
Unknown W. Brackets 463b2a90c7 irjit: Allow precompiling funcs at start. 
This can take a second, but cuts down on jitc spikes throughout runtime.
Note: bits of the game will still be recompiled as games change code.

This is basically the same operation as loading from cache, without the
cache yet.
 2018-01-06 17:06:53 -08:00
Unknown W. Brackets 6149ac584f jit: Add interface to precompile functions. 
This doesn't actually do any preloading yet, it just adds an API.
 2018-01-06 16:43:38 -08:00
Unknown W. Brackets ccd562d934 irjit: Add a safety check for block num overflow. 
In case a game is very frequently modifying some block.
 2018-01-04 23:24:15 -08:00
Unknown W. Brackets 0bfab27b46 irjit: Calculate bloat statistics. 
At least based on IR for now.  Can do something else later.

memset() was causing a crash on the std::map.
 2018-01-04 23:09:03 -08:00
Henrik Rydgård 2709472abd Merge pull request #10506 from hrydgard/ir-interpreter-simd 
More IR interpreter SIMD
 2018-01-05 01:21:32 +01:00
Henrik Rydgård 8c3a50d089 Merge pull request #10505 from hrydgard/ir-disasm-jit-compare 
Show IR disassembly in JIT Compare screen
 2018-01-05 01:20:49 +01:00
Henrik Rydgård d1d01bfdcb Cleanup GetBlockNumberFromStartAddress 2018-01-05 01:20:10 +01:00
Henrik Rydgård 331a8f91e8 Fix that weird unordered compare mode, hopefully 2018-01-04 20:06:26 +01:00
Henrik Rydgård 18be23eccc IR: More fixes. Still something wrong with VFPU compares (not caused by this PR). 2018-01-04 19:38:36 +01:00
Henrik Rydgård ca9050b84c On Linux, can't even include nmmintrin without explicitly enabling SSE 4.2 support. 2018-01-04 18:27:19 +01:00
Henrik Rydgård fe88d12055 IR interpreter: Add some braces to allow variable declaration in the switch cases. 2018-01-04 18:27:19 +01:00
Henrik Rydgård e0cc126d09 Add some more SIMD support to IR interpreter. Mostly just because, but also serves as implementation reference for later code generation backends. 2018-01-04 18:27:19 +01:00
Henrik Rydgård a128624f98 IRInterpreter: Fix bugs in floating point truncation functions 2018-01-04 18:25:54 +01:00