Henrik Rydgård and Claude Fable 5.1
b16cd9a734
VFPU: vsgn of a denormal is zero
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In the interpreter, the IR interpreter, every backend's FSign and the x86
JIT's own vsgn. Recorded in cpu/vfpu/specials.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com >
2026-09-22 14:10:22 -06:00
Henrik Rydgård
0e6fc8e0e3
Assorted warning fixes
2024-11-28 15:02:26 +01:00
Unknown W. Brackets
9b2fa46861
IR: Add mini native jit MIPS block profiler.
2023-09-24 23:04:29 -07:00
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14e2e1ed62
x64jit: Optimize FCmpVfpuAggregate.
2023-09-23 14:31:46 -07:00
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7a5cdafdf3
arm64jit: Implement convert/int conversions.
2023-09-08 00:03:12 -07:00
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b698c673a8
arm64jit: Implement FSat.
2023-09-08 00:03:12 -07:00
Unknown W. Brackets
5617d08620
arm64jit: Remove unused variable.
2023-09-07 17:26:30 -07:00
Unknown W. Brackets
178bb8416b
arm64jit: Implement FSpecial.
2023-09-06 20:08:36 -07:00
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fad24e3b44
arm64jit: Implement FSign.
2023-09-06 19:53:49 -07:00
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a1304f6ac8
arm64jit: Implement VFPU compare in IR.
2023-09-06 19:02:24 -07:00
Unknown W. Brackets
01ed48a3d0
arm64jit: Implement FCvtSW.
2023-09-06 00:09:26 -07:00
Unknown W. Brackets
89a9584c38
arm64jit: Implement FRound/similar.
2023-09-06 00:09:26 -07:00
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97d9a7f07f
arm64jit: Implement FCmp.
2023-09-06 00:09:26 -07:00
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c8f888fab0
arm64jit: Implement FMin/FMax.
2023-09-06 00:09:26 -07:00
Unknown W. Brackets
87b9633258
arm64jit: Add some simple float ops.
2023-09-03 21:14:58 -07:00
Unknown W. Brackets
1b756ff8c1
arm64jit: Add initial base for IR jit.
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This works, but very slowly at this point.
2023-09-03 12:14:28 -07:00