Henrik Rydgård and Claude Opus 5.5
a2b10778be
VFPU: vsqrt, vrsq, vrcp and vnrcp are exact in every backend
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These went through the host's sqrt and division everywhere except the
interpreter's vrcp and vnrcp (vsqrt and vrsq there only behind
USE_VFPU_SQRT, now gone). They now always give the PSP's bits: the IR
gets FVSqrt (FSqrt stays the FPU's IEEE sqrt.s), and FRSqrt and FRecip,
which only the VFPU emits, become vfpu_rsqrt and vfpu_rcp; the IR
interpreter and the x64, arm64, RISC-V and LoongArch backends call them.
The old JITs call them directly, the ARM ones keeping the lanes in
callee-saved registers across the calls. cpu/vfpu/exact now passes on every core.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-09-24 12:24:42 -06:00
Henrik Rydgård
67ddf899ba
Plumb through the PC value for syscalls, so we can get better diagnostics for unresolved ones.
2026-08-15 19:14:13 +02:00
Henrik Rydgård
ae14ebb6ac
IRWriter: Remove the confusing and inefficient AddConstant
2026-08-15 18:31:20 +02:00
Henrik Rydgård
45cf6d423e
Buildfixes
2024-12-18 13:57:29 +01:00
Nemoumbra
bd6c469543
Code-review fixes
2024-09-16 02:48:52 +03:00
Nemoumbra
f23b04fb4a
Logic errors fixed + refactoring
2024-09-14 19:46:05 +03:00
Nemoumbra
34f113207d
Added the MIPSTracer files to the project + name fix
2024-09-14 19:46:04 +03:00
Nemoumbra
a6be0517dc
New IR instruction added
2024-09-14 19:46:04 +03:00
Henrik Rydgård
d3e6f19b6d
Comments, log, cleanup
2024-07-22 01:15:35 +02:00
Henrik Rydgård
6ebec02f05
Fix crash in JITIR after disassembly improvement.
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Fixes #19292
2024-06-22 15:16:27 +02:00
Henrik Rydgård
c9ca3904d3
Combine move-from-gpr and float cast.
2024-06-08 22:59:48 +02:00
Henrik Rydgård
0c246297d2
Create an IR op for a FPRtoGPR + shift-right-8, very common
2024-06-07 21:26:20 +02:00
Henrik Rydgård
d1e0384b2f
Improve disasm
2024-06-07 19:32:37 +02:00
Henrik Rydgård
da88011805
Specialize a few arithmetic instructions for the interpreter.
2024-06-07 19:32:37 +02:00
Henrik Rydgård
a6f398a7d2
Add IRJit arena overflow check
2024-06-07 10:17:01 +02:00
Henrik Rydgård
d1a00f61de
Improve disassembly of CallReplacement IR op
2024-06-06 15:24:58 +02:00
Henrik Rydgård
e3177ac870
Make some global string pointers const, not just the strings.
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Minor cleanup.
2023-12-29 14:09:45 +01:00
Unknown W. Brackets
053831bf4d
HLE: Add mechanics for sliced replacements.
2023-12-16 09:08:58 -08:00
Unknown W. Brackets
1042737c21
irjit: Correct metadata on Vec2 packing ops.
2023-09-03 21:13:11 -07:00
Unknown W. Brackets
e1a1f56f4c
irjit: Cleanup breakpoint ops.
2023-09-03 12:27:10 -07:00
Unknown W. Brackets
f263698897
irjit: Cleanup temp purging on exit.
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We were sometimes considering it read by exit and not purging.
2023-08-27 12:26:05 -07:00
Unknown W. Brackets
cc4bc406d5
riscv: Cleanup VfpuCtrlToReg meta, use auto-map.
2023-08-20 12:42:11 -07:00
Unknown W. Brackets
2b36e0a625
irjit: ZeroFpCond -> FpCondFromReg.
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We already have a zero reg, so this is more useful and symmetrical.
2023-08-13 10:40:47 -07:00
Unknown W. Brackets
79ca880ac7
irjit: Implement vqmul, add Vec4Blend.
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Should be useful more places.
2023-08-06 13:38:00 -07:00
Unknown W. Brackets
b03398a46c
Merge pull request #17815 from unknownbrackets/riscv-jit
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riscv: Spill registers more intelligently
2023-07-30 14:49:37 -07:00
Unknown W. Brackets
f870271011
riscv: Spill registers more intelligently.
2023-07-30 14:24:12 -07:00
Unknown W. Brackets
f3240393fa
irjit: Use vf for vfpu regs, v0 is a gpr.
2023-07-30 14:16:17 -07:00
Unknown W. Brackets
6819acd29f
irjit: Fix flag on float cond move.
2023-07-30 14:16:17 -07:00
Henrik Rydgård
180bda6f6b
Merge pull request #17799 from unknownbrackets/irjit-lsu
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Add ll/sc to IR and x86jit
2023-07-30 09:15:55 +02:00
Unknown W. Brackets
e228748449
irjit: Add FCvtScaledSW to safely scale vi2f.
2023-07-29 18:30:15 -07:00
Unknown W. Brackets
a5a2671af3
irjit: Implement vf2ix.
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Used in LittleBigPlanet when playing intro movies.
2023-07-29 18:01:08 -07:00
Unknown W. Brackets
df2462b1d9
irjit: Implement ll/sc.
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These occur more than I expected in LittleBigPlanet while loading.
2023-07-29 17:57:44 -07:00
Unknown W. Brackets
df313bd296
riscv: Fix rounding mode setting.
2023-07-25 20:33:56 -07:00
Unknown W. Brackets
9157d992ac
jit-ir: Implement cfc1/ctc1.
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This makes it so we can track rounding mode changes.
2023-07-25 20:33:56 -07:00
Unknown W. Brackets
6da10463f9
Debugger: Make reg names safer, stop using v000.
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Better to use S000, etc. as that's more clear throughout.
2023-04-29 09:48:33 -07:00
Unknown W. Brackets
6715f41410
irjit: Add constructs for validing mem access.
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Basically to allow slow/fast memory to work with IR, including for
alignment checks.
2022-08-21 13:01:23 -07:00
Unknown W. Brackets
021f4adfad
irjit: Fix mtv for INF4.
2021-01-09 12:43:50 -08:00
Unknown W. Brackets
670334bd0c
irjit: Correct flags for SetCtrlVFPUReg.
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Fixes #13897 . Caused the reg to be optimized out.
2021-01-09 12:33:08 -08:00
Henrik Rydgård
3322adbc22
IR Interpreter: Add some missing instruction metadata. May help part of #10897
2018-04-11 11:16:41 +02:00
Unknown W. Brackets
6dda053365
irjit: Add dedicated ops for lwl/swl and friends.
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Temporarily removes optimizations.
2018-01-07 21:05:57 -08:00
Unknown W. Brackets
bc541bd020
irjit: Encode downcount directly as a constant.
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Simpler this way, now.
2018-01-03 23:32:31 -08:00
Unknown W. Brackets
cffb2d61a7
irjit: Embed constant inside IRInst.
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This simplifies a bunch of code and improves compile performance by about
30%, at the cost of a bit more memory.
2018-01-03 23:24:04 -08:00
Unknown W. Brackets
671be24105
irjit: Add extra temps to make lwl/swl/etc. easier.
2018-01-01 08:38:11 -08:00
Unknown W. Brackets
4578c3cb54
jit-ir: Implement memory breakpoints.
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These generally work, but likely delay slots will make downcount slightly
off, and won't resume when you hit run again without manually stepping
through them.
2016-07-02 16:38:30 -07:00
Unknown W. Brackets
6fb34d0bee
jit-ir: Add initial breakpoint support.
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No memory breakpoints yet, and cache isn't cleared yet so these don't work
exactly the way you might expect...
2016-07-01 17:15:57 -07:00
Henrik Rydgard
f544364c4a
Fix bug in vus2i (thanks unknown), recognize vectors in IR disasm
2016-05-15 23:35:33 +02:00
Henrik Rydgard
d6c2b6e9ae
Most of vi2x
2016-05-15 11:46:01 +02:00
Henrik Rydgard
905af75925
vx2i, vbfy, vsgn
2016-05-15 10:57:43 +02:00
Unknown W. Brackets
4ac773e8b4
jit-ir: Implement bit reverse instruction.
2016-05-14 18:21:42 -07:00
Henrik Rydgard
0541fe36df
Symbian buildfix, fix for fpu test
2016-05-14 15:26:43 +02:00
