Henrik Rydgård and Claude Opus 5.5
00f5e12b47
IR JIT: Don't store dead temps at exits
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The IR temps don't live past the block, but FlushAll stored them anyway at
every exit (the branch operands, lwl/lwr temps, VFPU temp lanes). At an exit,
discard the ones nothing later in the block reads.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-09-24 16:38:39 -06:00
Henrik Rydgård and Claude Opus 5.5
a99a82cc6b
IR: Keep more constants known in PropagateConstants
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- A constant stays known after it's written out for a read (by a store,
MovZ, a multiply...), so later uses still fold. Whatever an op writes is
forgotten after its inputs are written, and setting a reg to the value it
already holds isn't written twice.
- A conditional exit that isn't taken keeps the constants known.
- The saturating and min/max FP ops, FSign and the 31-bit Vec2 pack/unpack
no longer flush every GPR constant.
- A load through its own base is folded (lui v0, hi; lw v0, lo(v0)).
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-09-24 16:35:11 -06:00
Henrik Rydgård
0c077acc74
Do some include untangling, to limit the spread of the Windows.h include from SevenZipFileReader.h
2026-03-27 14:34:18 -06:00
Henrik Rydgård
1a89c26dc0
Warning fixes
2024-10-03 18:19:11 +02:00
Henrik Rydgård
5526ef012c
Store IR instructions in a large arena vector instead of loosely in each block.
2024-06-07 09:28:27 +02:00
Unknown W. Brackets
685d2acffe
x86jit: Retain old lanes when there's space.
2023-09-24 17:31:25 -07:00
Unknown W. Brackets
88b6442527
irjit: Add facility for native reg transfer.
2023-09-24 16:28:29 -07:00
Unknown W. Brackets
9bac755491
x86jit: Avoid pointerify if clobbered.
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For x86, it's not worth it for one.
2023-09-01 22:34:22 -07:00
Unknown W. Brackets
f10444eb42
x86jit: Special case broadcast shuffles.
2023-08-27 23:24:30 -07:00
Unknown W. Brackets
61a99b4bac
x86jit: Implement trig/reciprocals.
2023-08-27 23:24:30 -07:00
Unknown W. Brackets
363f2b68e1
x86jit: Implement shifts.
2023-08-25 00:01:03 -07:00
Unknown W. Brackets
07fa1ed573
x86jit: Automatically flush incompatible regs.
2023-08-21 21:16:54 -07:00
Unknown W. Brackets
db34b85107
irjit: Allow flag-based allocation order.
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Sometimes backends have needs, like XMM0/v0-only, or similar.
2023-08-21 20:46:05 -07:00
Henrik Rydgård
629d46ef5b
Merge pull request #17938 from unknownbrackets/riscv-centralize
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Centralize IR regcache from RISC-V
2023-08-20 23:47:02 +02:00
Unknown W. Brackets
36b6aa4728
riscv: Allow GPR "SIMD" without FPR SIMD.
2023-08-20 12:42:11 -07:00
Unknown W. Brackets
6a75e6712e
riscv: Use automapping for special cases too.
2023-08-20 12:42:11 -07:00
Unknown W. Brackets
a190793ad2
riscv: Simplify mapping for more instructions.
2023-08-20 12:42:11 -07:00
Unknown W. Brackets
e40ae60029
riscv: Mark normalized32 after mapping.
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It's less confusing to separate it.
2023-08-20 12:42:11 -07:00
Unknown W. Brackets
f9bf7de701
riscv: Use a single reg cache.
2023-08-20 12:42:11 -07:00
Unknown W. Brackets
a23ade8f75
riscv: Map IR regs based on metadata.
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Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
2023-08-20 12:42:11 -07:00
Unknown W. Brackets
32d8f6196f
irjit: Cut time flushing imm regs.
2023-08-20 08:59:47 -07:00
Unknown W. Brackets
161465ab66
riscv: Centralize register FlushAll().
2023-08-19 21:30:03 -07:00
Unknown W. Brackets
f3d4bd8c11
riscv: Centralize reg-as-pointer.
2023-08-19 21:24:36 -07:00
Unknown W. Brackets
92f7374c89
riscv: Centralize reg mapping itself.
2023-08-19 16:15:49 -07:00
Unknown W. Brackets
718a1b3944
riscv: Centralize MarkDirty flagging.
2023-08-19 16:15:49 -07:00
Unknown W. Brackets
4e41f83ecc
riscv: Centralize IR reg cache metadata checks.
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These are all largely the same between backends.
2023-08-17 23:03:31 -07:00
Unknown W. Brackets
ebab0e1591
riscv: Centralize reg allocation.
2023-08-17 18:50:33 -07:00
Unknown W. Brackets
b30daa5760
riscv: Centralize state of regcaches.
2023-08-15 21:51:38 -07:00
Unknown W. Brackets
5f9a8fd1a1
irjit: Rename IRRegCache to IRImmRegCache.
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For clarity, since it's not a native regcache.
2023-08-08 23:05:14 -07:00
Unknown W. Brackets
b2d3c750f1
irjit: Define a specific IRReg type.
2023-07-23 18:01:00 -07:00
Henrik Rydgard
d4480d50fd
jit-ir: Less instructions cause flushing in constant propagation.
2016-05-08 23:25:08 +02:00
Henrik Rydgard
14df39d7c9
Fix IRTEMP clash bug. Add more cases to the constant propagation pass.
2016-05-08 10:36:37 +02:00
Henrik Rydgard
09969c0156
Use the regcache in a new (incomplete) pass, PropagateConstants.
2016-05-08 01:06:07 +02:00
Henrik Rydgard
d399c4a470
Initial commit for IRJit
2016-05-07 13:58:29 +02:00
