preserve-emulation/ppsspp
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33,798 Commits 78 Branches 131 Tags
95d40cc09f86152b6ef6f00a09bc062cd3f5de67
Commit Graph
15 Commits
Author SHA1 Message Date
Sprite 0ed86188b0 Fix const pointer conversion error for RISC-V 2022-09-15 23:53:19 +08:00
Unknown W. Brackets 08d82ec15b riscv: Emit compressed instructions. 
Includes automatically using compressed, optionally.
 2022-08-27 15:44:19 -07:00
Unknown W. Brackets 946080206d riscv: Improve sign reduce/immediate readability. 2022-08-27 15:44:18 -07:00
Unknown W. Brackets c807d459f6 riscv: Emit ADD/SUB/etc. for ADDW/SUBW/etc. on R32. 
No need to complicate code, we can just write ADDW() and expect it to work
on R32 (if ever motivated to support it.)
 2022-08-27 15:44:18 -07:00
Unknown W. Brackets c81d887a86 riscv: Include an LI helper in the emitter. 
Can be used for integers and floats.
 2022-08-27 15:44:18 -07:00
Unknown W. Brackets 4a93647acb riscv: Emit CSR manipulation instructions. 2022-08-25 21:20:49 -07:00
Unknown W. Brackets b5755b6cf7 riscv: Validate FixupBranch usage better. 
Also avoid FixupBranch alignment issues.
 2022-08-25 21:20:49 -07:00
Unknown W. Brackets 591de6be1d riscv: Emit float instructions. 2022-08-25 21:19:28 -07:00
Unknown W. Brackets 53693072d2 riscv: Emit atomic operations. 2022-08-25 21:19:28 -07:00
Unknown W. Brackets c66d02d4db riscv: Emit mul/div instructions. 2022-08-25 21:19:28 -07:00
Unknown W. Brackets 00280ab2ad riscv: Emit fence and 64-bit instructions. 2022-08-25 21:19:28 -07:00
Unknown W. Brackets 49ec8a207d riscv: Emit 32-bit 3-op instructions, validate GPR. 2022-08-25 21:19:27 -07:00
Unknown W. Brackets 1c35cfb325 riscv: Emit 32-bit load/store and imm ops. 2022-08-25 21:19:27 -07:00
Unknown W. Brackets 1dab9d1875 riscv: Emit standard B/U/J type ops. 2022-08-25 21:19:27 -07:00
Unknown W. Brackets 9fcad83940 riscv: Add initial emitter shell. 2022-08-25 21:17:11 -07:00