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Code Issues Packages Projects Releases Wiki Activity
16,422 Commits 78 Branches 131 Tags
87be57a1fa525950809ff8ca320b2a3e803ff31d
Commit Graph
57 Commits
Author SHA1 Message Date
Henrik RydgårdandUnknown W. Brackets a897723e6a Separate out jit reading nearby instructions. 
This makes it easier to use an IR for these things, or remove them.
 2015-04-11 00:53:24 -07:00
Henrik Rydgard 05a8e2e35d Some work towards being able to build two JITs together 
This will be useful for testing/debugging, but not there yet.
 2014-12-13 21:13:54 +01:00
Henrik Rydgard 51d55bd645 Namespacing cleanup (it's bad to do "using namespace" in a header) 2014-12-07 14:44:15 +01:00
Henrik Rydgard 4457dca4c9 Rename the ARM Jit class to ArmJit 2014-12-07 14:25:22 +01:00
Unknown W. Brackets f6f943de63 jit: MAP_NOINIT should always mean MAP_DIRTY. 2014-11-29 00:14:08 -08:00
Unknown W. Brackets 5a89c17cf0 armjit: Allow R1 in regalloc, use LR as temp. 
LR should be safe, although it may make stack traces not work within jit,
they don't really tend to work anyway.
 2014-03-28 18:38:38 -07:00
Unknown W. Brackets ca0a8d0269 armjit: fix lwl/lwr from an imm address. 
Can't skip loading the reg value.  Likely cause of #5057, possibly other
bugs as well.
 2014-03-13 00:23:00 -07:00
Henrik Rydgård b2260149ae ARM Jit: Avoid materializing some unnecessary immediates in loads/stores 2014-03-03 14:33:22 +01:00
Henrik Rydgard 5a02ea9ff4 Fix cache instruction on ARM 2013-12-10 13:26:32 +01:00
Unknown W. Brackets 98fb2e0402 armjit: Refer to R11 as MEMBASEREG for clarity. 2013-11-14 23:37:48 -08:00
Unknown W. Brackets 67eaa2fd1c armjit: Optimize immediate load/stores in a row. 2013-11-10 16:32:48 -08:00
Unknown W. Brackets 7e46ee0b0f armjit: Replace MOVI2R with using the regcache. 
So that it can optimize the value with existing imms.

Not actually optimizing yet.
 2013-11-10 15:50:45 -08:00
Unknown W. Brackets 455a7e090d Compile the cache instruction to nothing. 
Was showing up in a few profiles, does nothing currently.
 2013-11-10 14:38:10 -08:00
Unknown W. Brackets b2c2a87511 Fix omitted CC_AL reset, fixes #4498. 
Was breaking non-fastmem lwl/lwr/etc.
 2013-11-10 09:24:40 -08:00
Unknown W. Brackets 3aa8706ae7 armjit: Optimize lwl/lwr against an imm address. 2013-11-09 08:43:48 -08:00
Unknown W. Brackets 4026944b02 armjit: Handle lwl/lwr (not pretty, though.) 2013-11-09 08:42:30 -08:00
Unknown W. Brackets cb3bb73148 armjit: Improve GPR typesafety. 2013-11-09 08:24:15 -08:00
Henrik Rydgard 502f772856 Add experimental mode to cache pointers in the arm jit. 
Turned off for now as it needs more work but seems quite promising already.
 2013-11-09 17:15:30 +01:00
Henrik Rydgard 309f904c0c Extract JitState into its own header (arm/x86) 2013-11-08 18:51:52 +01:00
Henrik Rydgard 32c95af820 ARM: Some zero-register fixes 2013-11-07 15:29:13 +01:00
Unknown W. Brackets 157b682344 Always use fastmem for sw/lw on SP. 2013-09-07 22:44:18 -07:00
Unknown W. Brackets 97aa1a631e Improve typesafety in the x86 regalloc. 2013-08-24 19:41:10 -07:00
Unknown W. Brackets 109ad17ac6 Use a typesafe struct for opcodes. 
Also, correctly read delayslots using Read_Instruction on ARM.
 2013-08-24 15:36:24 -07:00
Unknown W. Brackets 1ed8edb0d3 Avoid some dangerous hex constant widths. 2013-08-22 23:23:48 -07:00
Unknown W. Brackets 796d2c10c6 armjit: VRAM comes before RAM, fix slowmem check. 
Can't think of anything else, hopefully fixes #1021.
 2013-03-18 08:08:40 -07:00
Unknown W. Brackets b8eb526691 armjit: improve slowmem, fix vram check. 
Darn, copy/paste error.
 2013-03-16 20:31:51 -07:00
Unknown W. Brackets 6ef5f4c8dc armjit: Refactor slowmem path for reusing it. 2013-03-16 14:37:35 -07:00
Unknown W. Brackets 45b0b1203f armjit: No, LDR/STR do not update flags. 
Oops, had some other bug and thought this was the issue.
 2013-03-16 14:37:35 -07:00
Unknown W. Brackets de3713fc50 armjit: improve mem speed without fastmem. 2013-03-16 14:37:35 -07:00
Unknown W. Brackets 8f3904d32d armjit: Speed up imm addresses in slowmem mode. 2013-03-16 14:37:35 -07:00
Sacha 529803e429 Sonic's ArmEmitter changes (cross-project merge from Dolphin) 2013-03-14 12:47:29 +10:00
Sacha 8125d96ce1 Small update for shifted load/stores. Still disabled. 2013-03-07 01:04:41 +10:00
Sacha a8b6fca61b Separate codepaths for shifted load/stores and normal load/stores. Fix dirty regs. 2013-03-07 00:59:07 +10:00
Sacha ae3b881a7f Use correct args for Operand2(..) through armjit. Fix STR(..). 2013-03-07 00:59:07 +10:00
Sacha 268d16bd24 Use correct args for STR(..) throughout armjit. 2013-03-07 00:59:07 +10:00
Sacha 23fb88c5fe Enable optimisation codepath (left+right combines). 2013-03-07 00:59:07 +10:00
Henrik Rydgard 9f327985fc armjit: disable lwl/lwr/swl/swr 2013-03-05 23:09:26 +01:00
Sacha 5a134243a7 Armjit: Fix lwl, lwr and enable again. Thanks Sonic. 2013-03-06 03:28:28 +10:00
Sacha 7e67de3334 Armjit: Implement lwl, lwr, swl, swr in ARM JIT. lwr is currently disabled as it isn't working. 2013-03-06 02:11:36 +10:00
Sacha 9152d2f2bb Armjit: Optimise swl+swr and lwl+lwr cases that can be combined to a single sw or lw. Add shift flags to STR/LDR. Add EatInstruction to ArmJit. 2013-03-06 02:11:36 +10:00
Unknown W. Brackets ab05149dbf Add a few more CONDITIONAL_DISABLEs. 2013-03-03 01:44:33 -08:00
Henrik Rydgard 516ca8a0c4 Merge branch 'master' into armjit-fpu 
Conflicts:
	Core/MIPS/ARM/ArmJit.h
	Core/MIPS/x86/CompVFPU.cpp
	GPU/GLES/Framebuffer.cpp
 2013-02-28 23:56:28 +01:00
Sacha 8d4400fba1 ARMJIT: Clean up for load/stores 2013-02-27 22:17:38 +10:00
Sacha ff14815fda ARMJIT: Combine to one instruction for load/stores. 2013-02-27 19:45:01 +10:00
Sacha 2c59de95e9 JIT the signed load/store variants too 2013-02-27 18:05:45 +10:00
Sacha fe8b80c12e ARM JIT: Add and simplify some half-word load/store instructions. 2013-02-27 17:09:47 +10:00
Henrik Rydgard b0c160fa93 Fix armjit fpu load / store 2013-02-13 21:07:06 +01:00
Henrik Rydgard 78923f5538 Jit a little more (vfpu single load/store, transfer instructions) 2013-02-10 12:14:55 +01:00
Henrik Rydgard d8f4e27926 Rename ARMABI_MOVI2R to MOVI2R 2013-01-31 23:41:05 +01:00
Henrik Rydgard aabc0aa9ef Quick implementation of LV.Q and SV.Q in x86/x64 JIT 2013-01-25 19:50:30 +01:00