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114 Commits
Author SHA1 Message Date
Henrik RydgårdandClaude Opus 5 029d17edfc IR: fix FpCondFromReg operand slot, and some smaller IR bugs 
FpCondFromReg's meta is "_G", so the register is in src1 - which is where
every native backend, PropagateConstants and ReorderLoadStore read it.
But IRInterpret read it from dest, and Comp_VecDo3 wrote it to dest to
match. The other emitter passes (0, MIPS_REG_ZERO), so both fields are
zero there and the disagreement stayed hidden.

The result was that vsge/vslt, which save fpcond to IRTEMP_0 and restore
it afterwards, restored r0 (always zero) on the native IR JITs instead of
the saved value, losing any c.cond.s result live across them. Fixed both
the emitter and the interpreter to use src1.

Vec4Pack31To8's SSE2 path computed (v >> 24) << 1, which is (v >> 23)
with bit 23 forced to zero - the scalar and NEON paths both do
(v >> 23) & 0xFF. Shift left first instead. The pspautotests inputs all
happen to have bit 23 clear after the clamp, so this wasn't caught.

Also:
- Evaluate() didn't mask constant-folded shift amounts to 5 bits, though
  the neighbouring one-immediate path does.
- ApplyMemoryValidation only invalidated its address-check cache for ops
  with a 'G' destination, while Interpret and CallReplacement can write
  any GPR - both are barriers, so drop the whole cache when we see one.
- ReduceVec4Flush indexed isVec4 with (src2 & 3) instead of (src2 & ~3)
  for Vec4Scale; a missed optimization rather than a miscompile.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
 2026-09-19 10:31:33 -06:00
Henrik Rydgård ae14ebb6ac IRWriter: Remove the confusing and inefficient AddConstant 2026-08-15 18:31:20 +02:00
Henrik Rydgård e51c58716b Fix minor code issues flagged by PVS-Studio and reported by alphrixus. 2024-10-10 14:10:30 +02:00
Henrik Rydgård e01ca5b057 Logging API change (refactor) (#19324) 
* Rename LogType to Log

* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.

* Mac/ARM64 buildfix

* Do the same with the hle result log macros

* Rename the log names to mixed case while at it.

* iOS buildfix

* Qt buildfix attempt, ARM32 buildfix
 2024-07-14 14:42:59 +02:00
Henrik Rydgård 5bfc0259be Optimize away the redundant vector loads in the Wipeout games. 2024-06-08 23:22:58 +02:00
Henrik Rydgård c9ca3904d3 Combine move-from-gpr and float cast. 2024-06-08 22:59:48 +02:00
Henrik Rydgård 0abcd00372 IR Interpreter: Don't split up lone lwr/swr/lwl/swl instructions, the interpreter handles them faster. 2024-06-08 22:28:11 +02:00
Henrik Rydgård 0c246297d2 Create an IR op for a FPRtoGPR + shift-right-8, very common 2024-06-07 21:26:20 +02:00
Henrik Rydgård bd0beb68a4 Add new IR optimization pass, OptimizeLoadsAfterStores 2024-06-07 19:32:37 +02:00
Henrik Rydgård da88011805 Specialize a few arithmetic instructions for the interpreter. 2024-06-07 19:32:37 +02:00
Henrik Rydgård bdf7f5f40f IRInterpreter: Fix issue where we could accidentally optimize out CallReplacement ops. 2024-05-26 00:12:48 +02:00
Unknown W. Brackets 5e813e6bd6 irjit: Correct bad Vec4 overlap handling. 2023-10-14 20:54:40 -07:00
Unknown W. Brackets cd46f0b4cb irjit: Cache IR metadata lookups. 
This improves compilation performance, because all those lookups were
adding up.
 2023-09-30 15:56:53 -07:00
Unknown W. Brackets 69b8fb9bc2 irjit: Correct alignment checks against SP. 2023-09-23 13:15:06 -07:00
Unknown W. Brackets 739e474957 irjit: Improve dot and store vec4 interaction. 2023-09-01 22:35:59 -07:00
Unknown W. Brackets 2ca638868c irjit: Remove Vec4Scale/Vec4Dot aliasing in pass. 2023-09-01 22:35:59 -07:00
Unknown W. Brackets 96c90c19c6 irjit: Reduce unnecessary shuffles. 
If it's never used as a Vec4 again, it's often not worth it.
 2023-09-01 22:35:59 -07:00
Unknown W. Brackets 5f84887dea irjit: Add a pass to keep Vec4s in Vec4s. 2023-09-01 22:35:59 -07:00
Henrik Rydgård ae0af175de Merge pull request #18004 from unknownbrackets/x86-jit-minor 
x86jit: Small cleanup and tweaks, downcountInRegster, GetFPRLaneCount bugfix
 2023-08-29 08:01:47 +02:00
Unknown W. Brackets 14d871730f x86jit: Optimize slow memory. 2023-08-28 21:16:38 -07:00
Unknown W. Brackets 8e8605935e irjit: Detect subtract-to-zero as constant. 2023-08-28 21:09:56 -07:00
Unknown W. Brackets 4e90bd5070 x86jit: Use NEG more automatically for Sub x,0,y. 2023-08-28 21:09:56 -07:00
Unknown W. Brackets f263698897 irjit: Cleanup temp purging on exit. 
We were sometimes considering it read by exit and not purging.
 2023-08-27 12:26:05 -07:00
Unknown W. Brackets 552cd88938 irjit: Skip some work in PurgeTemps. 2023-08-20 08:59:47 -07:00
Unknown W. Brackets 57123e8f9e irjit: Reserve some arrays that churn. 
Improves IR compile time by around 20-30%.
 2023-08-20 08:59:47 -07:00
Henrik Rydgård 2cdcc413b7 Merge pull request #17898 from unknownbrackets/irjit-vfputemps 
irjit: Cleanup/purge FPU/VFPU temps
 2023-08-13 21:08:00 +02:00
Unknown W. Brackets 2b36e0a625 irjit: ZeroFpCond -> FpCondFromReg. 
We already have a zero reg, so this is more useful and symmetrical.
 2023-08-13 10:40:47 -07:00
Unknown W. Brackets fa53b80574 irjit: Cleanup/purge FPU/VFPU temps. 
A lot of cases are followed by an FMov that just moved the temp to a
regular register, from VFPU instructions playing safe about overlaps.
 2023-08-13 10:14:10 -07:00
Unknown W. Brackets 31ff23746c irjit: Prefer ExitToConst over ExitToReg. 2023-08-08 23:14:01 -07:00
Unknown W. Brackets 3f97545f99 irjit: Reduce exits from constants. 
This reduces bloat a bit, and may help with common funcs that enter short
loops.
 2023-08-08 23:05:14 -07:00
Unknown W. Brackets 5f9a8fd1a1 irjit: Rename IRRegCache to IRImmRegCache. 
For clarity, since it's not a native regcache.
 2023-08-08 23:05:14 -07:00
Henrik Rydgård e9431d0d1e Merge pull request #17859 from unknownbrackets/irjit-vec4 
irjit: Use Vec4 a bit more
 2023-08-06 23:05:33 +02:00
Unknown W. Brackets 79ca880ac7 irjit: Implement vqmul, add Vec4Blend. 
Should be useful more places.
 2023-08-06 13:38:00 -07:00
Unknown W. Brackets a32889d3ca irjit: Consistently dirty vfpuctrl in IR. 2023-08-06 08:36:19 -07:00
Unknown W. Brackets b03398a46c Merge pull request #17815 from unknownbrackets/riscv-jit 
riscv: Spill registers more intelligently
 2023-07-30 14:49:37 -07:00
Unknown W. Brackets f870271011 riscv: Spill registers more intelligently. 2023-07-30 14:24:12 -07:00
Unknown W. Brackets 5db6b11ef2 irjit: Cleanup self-fmovs. 
These were sometimes getting emitted.
 2023-07-30 14:16:17 -07:00
Henrik Rydgård 180bda6f6b Merge pull request #17799 from unknownbrackets/irjit-lsu 
Add ll/sc to IR and x86jit
 2023-07-30 09:15:55 +02:00
Unknown W. Brackets e228748449 irjit: Add FCvtScaledSW to safely scale vi2f. 2023-07-29 18:30:15 -07:00
Unknown W. Brackets a5a2671af3 irjit: Implement vf2ix. 
Used in LittleBigPlanet when playing intro movies.
 2023-07-29 18:01:08 -07:00
Unknown W. Brackets df2462b1d9 irjit: Implement ll/sc. 
These occur more than I expected in LittleBigPlanet while loading.
 2023-07-29 17:57:44 -07:00
Unknown W. Brackets 48586ed0ad irjit: Combine Load32Left/Right even on unaligned. 
This helps on devices that don't allow unaligned load/store.
 2023-07-29 17:57:25 -07:00
Unknown W. Brackets df313bd296 riscv: Fix rounding mode setting. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets 9157d992ac jit-ir: Implement cfc1/ctc1. 
This makes it so we can track rounding mode changes.
 2023-07-25 20:33:56 -07:00
Unknown W. Brackets 90517ace59 irjit: Validate alignment in slow memory mode. 2022-08-21 13:24:10 -07:00
Unknown W. Brackets 6715f41410 irjit: Add constructs for validing mem access. 
Basically to allow slow/fast memory to work with IR, including for
alignment checks.
 2022-08-21 13:01:23 -07:00
Unknown W. Brackets 7b081a61c8 irjit: Correct another PurgeTemps case. 
In this case:
  Mov A, B
  AndConst A, A, 1
  Load32 C, A, 0

Was still swapping the Load32 to B, not just the AndConst.

Fixes #15735.
 2022-07-27 19:38:16 -07:00
Unknown W. Brackets 5abf1362a2 irjit: Clarify PurgeTemps, guard a couple ops. 
Although I think we skip simplify passes on breakpoints entirely, safer to
exclude these ops.
 2022-07-27 19:36:53 -07:00
Unknown W. Brackets 2154f747fc irjit: Simplify more arithmetic to Movs. 
Later passes rely on things being Mov, so better to have them more often.
 2022-07-24 11:35:54 -07:00
Unknown W. Brackets 8f23025209 irjit: Add tests for IR passes. 2022-07-24 11:35:54 -07:00