Commit Graph
18 Commits
Author SHA1 Message Date
Henrik RydgårdandClaude Opus 5.5 53ac2c7c56 IR: Compile kernel loads and stores instead of interpreting them
Kernel code's loads and stores may reach hardware registers, which only the
interpreter handled, so the IR frontend sent every one of them (in kernel
blocks, only run by the VSH boot) to it.

They now become LoadKernel*/StoreKernel* IR ops (one per size, like the
plain loads and stores), which check at run time whether the address is
memory or a hardware register (MMIO). After constant
propagation, ResolveKernelMemory turns the ones at a constant address that's
plain memory into ordinary loads and stores, so only the hardware registers,
and addresses only known at run time, stay checked. The native JITs run the
two ops through their IR fallback. They're barriers, since a register access
has side effects, but can't change the GPRs, so constants stay known across.

The kernel mode check for MMIO moves to the interpreter, the only caller that
can run user code there. TestMMIO covers the new paths and which accesses
stay checked. Under --vsh, the JIT and the interpreter now make the same
unhandled register accesses, in the same numbers.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
2026-10-20 13:40:47 +02:00
Henrik Rydgård bd0beb68a4 Add new IR optimization pass, OptimizeLoadsAfterStores 2024-06-07 19:32:37 +02:00
Henrik Rydgård da88011805 Specialize a few arithmetic instructions for the interpreter. 2024-06-07 19:32:37 +02:00
Unknown W. Brackets 5f84887dea irjit: Add a pass to keep Vec4s in Vec4s. 2023-09-01 22:35:59 -07:00
Unknown W. Brackets 6715f41410 irjit: Add constructs for validing mem access.
Basically to allow slow/fast memory to work with IR, including for
alignment checks.
2022-08-21 13:01:23 -07:00
Unknown W. Brackets b11f00cead irjit: Combine lwl/lwr and swl/swr, like before.
Still want to inline the operation, because the backend shouldn't have to
redo it every time, and we want the temps cleaned up if possible.
2018-01-07 21:05:58 -08:00
Unknown W. Brackets b37ba9e599 irjit: Add options for compile/optimize steps.
This way the backend can set flags for the type of IR it wants.  It's
seems too complex to combine certain things like lwl/lwr in a pass.
2018-01-01 08:38:12 -08:00
Unknown W. Brackets 5534fba72c jit-ir: Add load/store reorder and merge passes.
Can do more in merge, potentially.  Maybe it's not useful...
2016-05-17 21:24:13 -07:00
Henrik Rydgard 91a6cf5e44 Add a couple more passes (2-op, optimize f<->v fp moves) 2016-05-13 20:14:03 +02:00
Unknown W. Brackets 9f183c97ba jit-ir: Prevent reading ahead for each reg write. 2016-05-12 18:30:55 -07:00
Unknown W. Brackets 99468c6fc1 jit-ir: Optimize out unused temp regs.
This way, if constants have made the temp obsolete (common with ins, for
example), it won't even get set anymore.
2016-05-12 18:30:53 -07:00
Henrik Rydgard 2cbfb192c4 IR: Lots more VFPU support, some with SIMD 2016-05-12 12:17:25 +02:00
Unknown W. Brackets f6d245f3c4 jit-ir: Remove redundant simplify pass.
This is just doing the same thing as the const folding pass, really.
2016-05-09 00:13:01 -07:00
Unknown W. Brackets 0d7f151167 jit-ir: Add a utility func for applying passes. 2016-05-08 16:08:35 -07:00
Henrik Rydgard 14df39d7c9 Fix IRTEMP clash bug. Add more cases to the constant propagation pass. 2016-05-08 10:36:37 +02:00
Henrik Rydgard 09969c0156 Use the regcache in a new (incomplete) pass, PropagateConstants. 2016-05-08 01:06:07 +02:00
Henrik Rydgard 750d520cc7 Initial work on mult and friends. Fix another bug. 2016-05-07 22:27:58 +02:00
Henrik Rydgard 4acf85aa06 It's kind of starting to run 2016-05-07 17:37:19 +02:00