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5 Commits
Author SHA1 Message Date
Henrik Rydgård 22ac7ad119 MemFault: move RISC-V and LoongArch fault analysis out of HandleFault 
The RISC-V branch had its instruction-decode logic (including a locally
defined info struct) written directly inline in HandleFault(), unlike
the other three architectures which each delegate to a dedicated
AnalyzeLoadStore function in their disassembler file. Move it into
ext/riscv-disas.h/.cpp as RiscVAnalyzeLoadStore, matching the existing
X86AnalyzeMOV/Arm64AnalyzeLoadStore/ArmAnalyzeLoadStore pattern.
 2026-08-11 22:36:47 +02:00
Henrik Rydgård 2e85eb5128 More static code analysis fixes 2024-10-28 17:59:06 +01:00
Unknown W. Brackets 71fcc4a658 riscv: Fix disassembly of ra-relative jump. 2023-08-12 09:53:38 -07:00
Unknown W. Brackets 0d0029fc9d riscv: Add bitmanip ops to disasm. 2023-07-30 17:45:36 -07:00
Unknown W. Brackets 77849d3eed riscv: Add disassembler. 
From https://github.com/anthony-coulter/riscv-disassembler.
Modified slightly to pull in less headers in the h, prefix funcs.
 2023-01-01 10:28:53 -08:00