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14,671 Commits 78 Branches 131 Tags
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100 Commits
Author SHA1 Message Date
Unknown W. Brackets 5a89c17cf0 armjit: Allow R1 in regalloc, use LR as temp. 
LR should be safe, although it may make stack traces not work within jit,
they don't really tend to work anyway.
 2014-03-28 18:38:38 -07:00
Unknown W. Brackets b53143bb33 Revert "armjit: Skip an AND for rotate shifts." 
This reverts commit ab2dd54ade.

Even though the docs say it's safe but apparently not always.
 2014-03-22 15:54:48 -07:00
Unknown W. Brackets ab2dd54ade armjit: Skip an AND for rotate shifts. 2014-03-15 00:49:18 -07:00
Unknown W. Brackets bed9c82d0a armjit: Try to use nearby immediates in slti/u. 2014-03-14 19:26:52 -07:00
Unknown W. Brackets e783627947 armjit: Use our I2R funcs on reg/reg math too. 
When one is a known immediate.  This should catch more cases, like:

ori v0, $0, 0xFFFF
and v1, v1, v0
 2014-03-14 19:15:43 -07:00
Unknown W. Brackets 8e979da0f9 armjit: Use our I2R arm optimizations. 
Should help cases of ori and andi most, but also addiu.  They will all try
to use an optimized immediate (from another nearby value) if possible.
 2014-03-14 19:15:43 -07:00
Unknown W. Brackets c229232236 armjit: Specifically optimize check for negative. 2014-03-14 19:15:39 -07:00
Unknown W. Brackets 628390f3fa armjit: Tiny optimization for cast to short. 
See these sometimes in code, skip the load of R0 when we can.
 2014-03-14 19:15:39 -07:00
Henrik Rydgard 23e57b71e0 Revert "Shave one instruction off slti and slt on ARM." 
This reverts commit 04742e00fc.
 2013-11-30 16:06:16 +01:00
Henrik Rydgard 04742e00fc Shave one instruction off slti and slt on ARM. 2013-11-30 15:53:21 +01:00
Unknown W. Brackets dffa35ef2f When ins is used with a zero argument, don't OR. 
Seems it's used effectively to mask out bits with rs=zero.  Makes sense...
 2013-11-29 09:17:12 -08:00
Unknown W. Brackets c50ab6d6aa armjit: Fix divu when divisor is a constant 1. 
Fixes #4539 and #4520.
 2013-11-19 13:24:15 -08:00
Henrik Rydgard 4e0520131a Tiny optimization 2013-11-15 20:32:23 +01:00
Henrik Rydgard d17a5fefea ARM: Fix divide by 0 in software divide used on CPUs without HW divide. 2013-11-15 20:24:20 +01:00
Sacha 20e8a81268 Switch to compile-time ARMV7 define. 2013-11-15 11:20:39 +10:00
Henrik Rydgard 9a14d33372 Disable software divide that appears to be buggy, see #4539 2013-11-14 17:25:02 +01:00
Unknown W. Brackets ca7b2b554b armjit: fix major typo breaking mult/multu. 2013-11-10 21:54:44 -08:00
Unknown W. Brackets 7e46ee0b0f armjit: Replace MOVI2R with using the regcache. 
So that it can optimize the value with existing imms.

Not actually optimizing yet.
 2013-11-10 15:50:45 -08:00
Unknown W. Brackets 285ec1fad5 armjit: Implement mult/multu for immediates. 
Uncommon, but may reduce instructions a bit.
 2013-11-10 14:38:09 -08:00
Unknown W. Brackets 9bec82873c armjit: inline byteswaps of imm values. 2013-11-10 14:38:08 -08:00
Unknown W. Brackets 06c8cb9174 armjit: Do shifts with imms as much as possible. 
This may even make an imm operand2 safe that wasn't before.
 2013-11-10 14:38:08 -08:00
Unknown W. Brackets a3a061a69f armjit: Optimize a division by a power of two. 
These really happen.
 2013-11-09 08:43:53 -08:00
Unknown W. Brackets 1776c85882 armjit: Implement a software divide for divu. 
It's not actually that much code.
 2013-11-09 08:43:52 -08:00
Unknown W. Brackets b2a240d105 armjit: Implement msub/msubu. 2013-11-09 08:43:52 -08:00
Unknown W. Brackets cb3bb73148 armjit: Improve GPR typesafety. 2013-11-09 08:24:15 -08:00
Unknown W. Brackets 945b8bf5c5 armjit: optimize reverse subtract, avoid temp imms. 
If we have a non-op2 imm, get rid of it asap.  If we have a op2 friendly
imm, keep it.
 2013-11-09 08:18:43 -08:00
Unknown W. Brackets 415f22ecac armjit: Preserve imms on min/max as well. 2013-11-09 08:18:43 -08:00
Unknown W. Brackets 5d46a82f43 armjit: Use a MOV for add/or with 0. 
Might skip the ALU, so might be faster.
 2013-11-08 11:41:57 -08:00
Unknown W. Brackets b8e126e7ce armjit: Preserve imms in slt/sltu as possible. 2013-11-08 11:41:57 -08:00
Unknown W. Brackets 8393d4aaae armjit: Preserve immediates more in nor. 2013-11-08 11:41:56 -08:00
Unknown W. Brackets d7e42b26a3 armjit: Avoid flushing imm on add t0, imm, imm. 2013-11-08 11:41:56 -08:00
Unknown W. Brackets a435c9dd13 armjit: Optimize movz/movn with immediates. 2013-11-08 11:41:55 -08:00
Unknown W. Brackets 376918c408 armjit: Reverse add t0, N, t1 to preserve imm. 2013-11-08 11:41:55 -08:00
Unknown W. Brackets 02dd250354 armjit: Optimize out a few immediate logic cases. 2013-11-08 11:39:24 -08:00
Henrik Rydgard 309f904c0c Extract JitState into its own header (arm/x86) 2013-11-08 18:51:52 +01:00
Henrik Rydgard 32c95af820 ARM: Some zero-register fixes 2013-11-07 15:29:13 +01:00
Sacha 81d3df0841 ARMJIT: Minor optimisations for armv6 and armv7. 2013-11-06 15:28:26 +10:00
Sacha a5011e3ff0 Improve swap usage in MIPS. ARMv6 can use REV/REV16. Intepreter can use existing swap functions. 2013-11-06 01:20:35 +10:00
Unknown W. Brackets 97aa1a631e Improve typesafety in the x86 regalloc. 2013-08-24 19:41:10 -07:00
Unknown W. Brackets 109ad17ac6 Use a typesafe struct for opcodes. 
Also, correctly read delayslots using Read_Instruction on ARM.
 2013-08-24 15:36:24 -07:00
Sacha 2450c0d28d We can't use S2 or D1. Use alternative means. 2013-06-10 19:28:53 +10:00
Sacha 6712de1136 Armjit: Implement wsbh and wsbw (rev16 and rev). Fix encoding for rev16. 2013-06-05 11:32:44 +10:00
Sacha a14a2fafa9 ARMJIT: Fix and use DIV, DIVU, INS and EXT (ARMv7 and VFPv4 implementations). 2013-05-24 08:26:19 +10:00
Sacha 471ddd6380 Simplify armjit. 2013-03-26 02:41:15 +10:00
Henrik Rydgard 216dc7ad65 Optimize some common ops for immediates 2013-03-10 00:48:44 +01:00
Unknown W. Brackets a589361b82 Call GEtImm() before Map* in case of overlap. 2013-03-09 14:39:17 -08:00
Unknown W. Brackets 9100c4a5a2 armjit: Don't MapReg before checking for IsImm(). 2013-03-09 11:57:02 -08:00
Sacha 6adb6762f2 Enable instructions: ceil, ins (confirmed working). Buildfix for Qt platforms. 2013-03-08 12:36:04 +10:00
Unknown W. Brackets 925e4e42bd armjit: Disable ext for now, breaks Disgaea? 2013-03-07 02:08:45 -08:00
Unknown W. Brackets 028e85dc92 Cleanup some differences between the two jits. 2013-03-07 02:08:44 -08:00