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Author SHA1 Message Date
Henrik RydgårdandClaude Opus 5.5 f0ab8a0062 IR native backends: Fix ll into $zero, and sc losing its result 
ll into $zero mapped $zero for writing, which asserts. On ARM64 and
x86-64, sc wrote its 0/1 result into rt without marking it dirty, so it
was never stored (RISC-V and LoongArch already did this right).

See docs/cpu-equivalence.md.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
 2026-10-14 00:10:00 +02:00
Lin Runze 1d910b81ff loongarch: Add emitter, JIT and disassembler support for LoongArch64 2025-07-12 03:21:23 +08:00