11 Commits

Include renames

Author	SHA1	Message	Date
Henrik Rydgard	3b9e6243eb	Only flush the required registers on function calls (only implemented for real on ARM)	2013-07-28 22:21:43 +02:00
Unknown W. Brackets	2d15eb2acd	Re-enable lwl/lwr/swl/swr on the x86 jit. ... Now correctly handling ECX on x64.	2013-07-06 01:21:52 -07:00
Unknown W. Brackets	64c42ffaf2	Fix some warnings generated by clang.	2013-02-24 10:23:31 -08:00
Henrik Rydgard	68991511ee	Split out the FPU reg cache into its own file too.	2013-01-26 01:34:19 +01:00
Henrik Rydgard	ad5e2b58c6	Separate the two regcaches before doing major surgery to FPURegCache.	2013-01-26 01:34:18 +01:00
Unknown W. Brackets	ce5f393fb8	Hit immediates in the ALU better and more simply.	2013-01-25 00:16:55 -08:00
Unknown W. Brackets	df06bb5624	Add some checks to make sure ZERO is never set.	2013-01-20 19:48:53 -08:00
Henrik Rydgard	93470e0c1f	Remove some old PowerPC references...	2013-01-05 19:52:11 +01:00
Henrik Rydgård	ed68dea0d5	JIT: Ignore branches in delay slots. Not sure if this is 100% correct.	2012-12-26 08:37:53 +01:00
Henrik Rydgard	64cc573703	Switch to "GPL 2.0 or later" for various reasons. I wrote most of the code I imported from Dolphin (which is GPL2-but-not-later), so it should be OK.	2012-11-04 23:24:00 +01:00
Henrik Rydgard	4f7ad15758	Add snapshot of the whole source code.	2012-11-01 16:19:01 +01:00