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15,293 Commits 92 Branches 131 Tags
1dca8bcc9268eceaa1e04015effcaae4860e2f90
Commit Graph
65 Commits
Author SHA1 Message Date
Unknown W. Brackets 9dd6bb56bb jit: Make available js_ and jo_ in regcaches. 2014-12-07 21:07:23 -08:00
Henrik Rydgard 51d55bd645 Namespacing cleanup (it's bad to do "using namespace" in a header) 2014-12-07 14:44:15 +01:00
Henrik Rydgard e3a81f4346 x86 Jit: Basic implementation of vbfy1/2 (mostly to just cross another one off the list..) 2014-12-04 00:18:58 +01:00
Unknown W. Brackets 48b3a292d7 x86jit: Add more sanity checks. 2014-11-30 17:43:07 -08:00
Unknown W. Brackets 9cfe801075 x86jit: Ensure we don't sequence temps+regs. 2014-11-30 17:42:43 -08:00
Unknown W. Brackets 23e3916a77 x86jit: Fix a stupid typo. 2014-11-30 17:42:02 -08:00
Unknown W. Brackets c6b090d82e x86jit: When storing, verify alignment. 2014-11-30 13:06:16 -08:00
Unknown W. Brackets fbc453b083 x86jit: Oops, here also. 
Maybe I should kill these early returns after all..
 2014-11-30 12:39:30 -08:00
Unknown W. Brackets 5758102be6 x86jit: Correct handling of temp vregs in VS. 2014-11-30 12:33:06 -08:00
Unknown W. Brackets 750f40e260 x86jit: Oops, forgot to add this back. 
MapRegV() will be too dangerous if it locks so do it here.
 2014-11-30 11:02:55 -08:00
Unknown W. Brackets 0000be1bb2 x86jit: Add a MAP_NOLOCK flag to not lock. 
Only for MapRegs*.  And then lock all by default, including
TryMapRegsVS().
 2014-11-30 10:36:44 -08:00
Unknown W. Brackets 52cfe4a8a3 x86jit: Avoid MOVSS into self. 2014-11-30 10:35:26 -08:00
Henrik Rydgard ac772f25ff x86 JIT: Join adjacent vrot calls together to avoid redundant sin/cos calls. Add a prototype, fix minor issues. 2014-11-30 11:04:13 +01:00
Henrik Rydgård 7deb8055ee Merge pull request #7117 from unknownbrackets/jit-simd 
x86jit: Implement vmmov using SIMD
 2014-11-30 09:24:22 +01:00
Unknown W. Brackets 679a824487 x86jit: when reusing a reg, don't zap slot. 
If we returned the same reg it was in before, don't zap the slots because
slot #1 may be valid.
 2014-11-29 23:11:50 -08:00
Unknown W. Brackets c3578bd8eb x86jit: Find the correct available regs. 
If there aren't n available regs, they may not of course be in slots 0 and
1.  Have to go and find them.
 2014-11-29 22:12:40 -08:00
Unknown W. Brackets df6a07f24e x86jit: Allow only one reg for sequential load. 2014-11-29 22:11:52 -08:00
Unknown W. Brackets bb26e4f7d0 x86jit: Implement vmmov using SIMD. 
4x -> 87x in microbenchmarking.
 2014-11-29 18:46:38 -08:00
Unknown W. Brackets 67608639c5 x86jit: Oops, can't have loaded regs here yet. 2014-11-29 09:07:25 -08:00
Unknown W. Brackets f6f943de63 jit: MAP_NOINIT should always mean MAP_DIRTY. 2014-11-29 00:14:08 -08:00
Unknown W. Brackets 0839ce59e1 x86jit: Apply dirty when reusing 1-reg VS. 2014-11-27 01:05:11 -08:00
Unknown W. Brackets bbeb5758b7 x86jit: Simplify VS() / VSX() usage. 2014-11-27 00:07:17 -08:00
Unknown W. Brackets 039510a3e3 x86jit: Respect dirty even for non-simd. 2014-11-26 23:29:20 -08:00
Unknown W. Brackets f63c165f64 x86jit: Fix several cases of missing dirty checks. 2014-11-26 23:28:14 -08:00
Henrik Rydgard becdb14a3f x86 jit: Fix a couple issues in simd storefromregister 2014-11-26 22:25:18 +01:00
Henrik Rydgård 80797dc723 Merge pull request #7108 from unknownbrackets/jit-simd 
Fix the simd issue at least for Wipeout
 2014-11-26 21:42:02 +01:00
Unknown W. Brackets e5dabaabe2 x86jit: Optimize simd->non for 1-lane a little. 2014-11-26 09:20:50 -08:00
Unknown W. Brackets 5d0c32d1e6 x86jit: Assume non-simd regs are dirty. 2014-11-26 09:19:50 -08:00
Henrik Rydgard 804de50711 x86 jit: SIMD-ify VFPU register file writebacks where possible 2014-11-26 01:33:05 +01:00
Henrik Rydgard b3c8a82c49 x86 jit: SIMD-ify some more 2014-11-25 23:56:46 +01:00
Unknown W. Brackets ab7dd0df25 x86jit: Add an option to enable/disable vpfu simd. 2014-11-17 20:37:27 -08:00
Unknown W. Brackets 921b39ebf5 x86jit: Optimize a 2-reg simd load. 2014-11-16 15:05:17 -08:00
Unknown W. Brackets e68eb0a292 x86jit: Load sequential regs in one shot. 2014-11-16 15:05:17 -08:00
Unknown W. Brackets ed501302a2 x86jit: Add a check to see if we can map simd. 2014-11-16 15:05:16 -08:00
Unknown W. Brackets 27148d3712 x86jit: Add some helpers to check state. 2014-11-16 13:33:16 -08:00
Unknown W. Brackets de566be2ce x86jit: Split out the logic for loading simd regs. 2014-11-16 13:33:15 -08:00
Unknown W. Brackets 5347431c20 x86jit: Initial simd for VecDo3(). Broken. 
I'm not sure why/where it's broken...
 2014-11-16 13:33:15 -08:00
Unknown W. Brackets aad505e7b3 x86jit: Add a TryMapDirtyInInVS() for 3-op. 2014-11-16 13:33:14 -08:00
Unknown W. Brackets 88a753eff3 x86jit: Add an invariant contract to the fpu cache. 
This should help catch things better in debug mode.
 2014-11-16 13:33:14 -08:00
Unknown W. Brackets 4335bf3346 x86jit: Add basic mapping of SIMD regs. 
Not tested yet, just sketched out.  All very suboptimal.
 2014-11-16 13:33:13 -08:00
Unknown W. Brackets 9429359b47 x86jit: Add fallbacks when moving from VS -> V. 2014-11-16 13:33:12 -08:00
Unknown W. Brackets 2862367927 x86jit: Add force-non-simd to all current ops. 
Unless they already use MapRegs, because that will automatically handle
it.
 2014-11-16 13:33:12 -08:00
Unknown W. Brackets 4cf0913692 x86jit: Sketch some initial SIMD apis. 2014-11-16 13:33:07 -08:00
Henrik Rydgård eab010a0c0 x86 JIT: Sacrifice a register for a pointer to the MIPS context. Shrinks emitted x86 code considerably. 
Nice in 64-bit, but might be a bit too much in 32-bit though... Needs testing.
 2014-10-12 19:35:55 +02:00
Unknown W. Brackets 3001866d18 Skip flushing FPU/VFPU regs if none were allocated. 
They're not used as often, so this usually saves time.  About 1% during
tests.
 2014-03-30 00:42:25 -07:00
The Dax 21ce99cabd Fix Unix-like builds. 2014-03-15 10:02:47 -04:00
Henrik Rydgard f9f6e9492d Reorder vfpu data in saved kernel contexts when loading in a new version. 2013-11-28 13:27:51 +01:00
Henrik Rydgard 55500d4bb6 Reorder VFPU registers in memory so that we can flush and reload them in bulk more often. 
Doesn't actually do that yet, that's for the NEON branch.
 2013-11-28 13:27:51 +01:00
Henrik Rydgard 5ad04a23f4 x86 jit: Rename BindToRegister to MapReg 2013-11-09 15:23:31 +01:00
Unknown W. Brackets 95c68ae1e7 Assert some unlikely buffer overflows. 2013-10-26 18:30:55 -07:00