Henrik Rydgård
e979b3a6ce
Merge pull request #7696 from unknownbrackets/texcache2
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Unswizzle when reading from the swizzled mirror
2015-04-19 10:27:29 +02:00
Henrik Rydgård
52b7bab829
Merge pull request #7698 from unknownbrackets/bezier-minor
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Try to optimize bezier color sampling
2015-04-19 10:24:39 +02:00
Henrik Rydgård
9f7554c08f
Merge pull request #7699 from unknownbrackets/d3d9
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d3d9: Clear the stencil/alpha on buffer reformat (matching GLES)
2015-04-19 10:23:15 +02:00
Unknown W. Brackets
2e4d20883f
d3d9: Reset viewport when clearing framebuf.
2015-04-18 17:40:21 -07:00
Unknown W. Brackets
eb98d89fc9
d3d9: clear alpha on switch from 565 buffer.
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For parity with OpenGL.
2015-04-18 17:39:18 -07:00
Unknown W. Brackets
b12a595325
d3d9: Make sure to clear alpha to zero.
2015-04-18 17:39:18 -07:00
Unknown W. Brackets
5ee062c681
Try to optimize bezier color sampling.
2015-04-18 12:47:21 -07:00
Unknown W. Brackets
b726a414d7
Log a reason when invalidating textures.
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Makes debugging easier.
2015-04-18 12:42:13 -07:00
Unknown W. Brackets
58563324bd
Include texture size in cache key.
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This makes Tales of Destiny 2's towns significantly faster. It may
however cause us to keep textures around for longer - but we still account
for them in our metrics and invalidation.
2015-04-18 12:42:13 -07:00
Unknown W. Brackets
ce9f404bef
Unswizzle when reading from the swizzled mirror.
2015-04-18 12:39:04 -07:00
Unknown W. Brackets
49783edf6d
Reorganize travis, disable Symbian, add Qt.
2015-04-18 01:12:23 -07:00
Unknown W. Brackets
327ca4c96e
Stub invalid vertex decoder colors to avoid crash.
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These values are invalid, but before we'd call a null pointer if we hit
them. Should do tests to see what actual behavior is.
2015-04-17 23:24:21 -07:00
Unknown W. Brackets
42bcea7b41
Report when minz/maxz is used in an effective way.
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As long as it's outside the viewport it should be clipped anyway.
One concern is, does clipenable affect z? A game could depend on that.
2015-04-17 12:59:59 -07:00
Henrik Rydgard
a9ff7c22fe
Reject too-small spline patches. Might help #7690 .
2015-04-17 08:33:05 +02:00
Unknown W. Brackets
5d704e48c1
Merge pull request #7688 from hrydgard/spline-fix
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Workaround crashes in spline code, fixing #7684
2015-04-16 09:45:07 -07:00
Henrik Rydgard
68893c763f
Spline: Fix an unrelated kind-of-bug
2015-04-16 18:32:37 +02:00
Henrik Rydgard
6587f4de8f
Spline: Fix #7684 by removing awful epsilons that "fixed" off-by-ones depending on vertex count because of fp rounding.
2015-04-16 18:32:13 +02:00
Henrik Rydgard
2e38762708
Spline: Add commented-out sanity check for debugging
2015-04-16 18:22:08 +02:00
Henrik Rydgard
b3305246a3
Spline: Not that it should matter, but move the patch_div clamping down after the subsampling
2015-04-16 18:18:49 +02:00
Henrik Rydgard
6bc9a525f8
Spline: remove n and m, confusing
2015-04-16 18:14:46 +02:00
Unknown W. Brackets
b818509734
x86jit: Fix clobbering address in lv.q/sv.q.
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We can't let it go into EAX. Hmm, maybe there's a cleaner way.
Should fix #7686 .
2015-04-14 23:17:11 -07:00
Unknown W. Brackets
4aa92ed99e
Read fcr1-30 as 0.
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Accidentally broken in 91966824bb
2015-04-13 19:09:53 -07:00
Unknown W. Brackets
8effb3e3a7
Try new Travis Ubuntu version.
2015-04-13 18:49:30 -07:00
Henrik Rydgård
a1f5c537d4
Merge pull request #7672 from unknownbrackets/jit-minor
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More x86jit micro optimizations for the FPU
2015-04-13 09:57:02 +02:00
Henrik Rydgård
1b0a9a48ae
Merge pull request #7683 from unknownbrackets/clut-align
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Fix clut load alignment and access outside valid memory
2015-04-13 09:34:54 +02:00
Unknown W. Brackets
67662ee23f
Force clut address to align to 16.
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Hardware seems to ignore the lower bits when loading.
2015-04-12 22:39:49 -07:00
Unknown W. Brackets
1e8f2c2630
Allow clut load outside valid mem, fill with zero.
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And only for the parts outside memory.
2015-04-12 22:38:17 -07:00
Unknown W. Brackets
391ca8bed3
Add functions to validate memory ranges.
2015-04-12 22:37:55 -07:00
Henrik Rydgård
ca14497111
Merge pull request #7680 from unknownbrackets/ir-parts
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Even more parts of the jit-ir branch
2015-04-12 23:02:43 +02:00
Henrik Rydgård
c1b91ff5c1
x86: Add a way to eliminate some mov instructions.
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Not currently used yet.
2015-04-12 13:50:23 -07:00
Henrik Rydgård
70fa830ba5
Split out the ReplaceJalTo test logic.
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This makes it so the IR, in the future, can work correctly for
replacements.
2015-04-12 13:35:10 -07:00
Henrik Rydgård
c6113b831d
Remove unused and duplicate define.
2015-04-12 13:16:01 -07:00
Henrik Rydgård
f81781d25c
Unify JitOptions in FakeJit also.
2015-04-12 13:15:00 -07:00
Unknown W. Brackets
2107771347
Oops, typo.
2015-04-12 13:12:31 -07:00
Henrik Rydgård
45f259178b
Merge pull request #7679 from unknownbrackets/ir-parts
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More parts of the jit-ir branch
2015-04-12 21:40:01 +02:00
Henrik Rydgård
18769f6ff4
Merge pull request #7678 from unknownbrackets/fbcopy
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Add a bit of a hack for smaller framebuf memcpys
2015-04-12 21:38:45 +02:00
Henrik Rydgård
a8b50d0c9b
Fix MIPSInfo masking for 64-bit flags.
2015-04-12 11:57:49 -07:00
Henrik Rydgård
6dcf56530b
Add some missing FPU flags to MIPSTables.
2015-04-12 11:56:04 -07:00
Henrik Rydgård
071b6b986a
Best-effort update of the MipsJit prototype
2015-04-12 11:53:16 -07:00
Unknown W. Brackets
0818c77f11
Normalize case of MIPS/ in MSVC project files.
2015-04-12 11:46:35 -07:00
Henrik Rydgård
bf7969e5b5
Add MipsJit to the MSVC project files.
2015-04-12 11:45:29 -07:00
Henrik Rydgård
d014d420db
Unify JitOptions across the backends.
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This is required to make ExtractIR not a member of the various backends.
2015-04-12 11:41:26 -07:00
Henrik Rydgård
7bf67509d1
ARM: Cleanup a TODO in NEON VFPU.
2015-04-12 11:21:53 -07:00
Unknown W. Brackets
be7d1d1169
Add a bit of a hack for smaller framebuf memcpys.
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Hopefully this doesn't false-positive in any other games. Helps Valkyrie
Profile's battle entry effect.
2015-04-12 11:05:28 -07:00
Unknown W. Brackets
ffe7ef1ee2
Avoid spurious warnings in sceAtrac.
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Valkyrie Profile for example calls this, doesn't seem like 0 matters.
2015-04-12 10:35:53 -07:00
Henrik Rydgård
6deb4d303d
Merge pull request #7675 from vnctdj/master
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Change translation category
2015-04-12 11:46:09 +02:00
vnctdj
e27bf8567e
Change translation category
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https://github.com/hrydgard/ppsspp/commit/59d0baca9375fa094d81fe465abd99efdcd97885#diff-a79dfbd66a9e1e1dc097bc65fc5f7027R570
2015-04-12 11:23:57 +02:00
Henrik Rydgård
0bf482231b
Merge pull request #7673 from unknownbrackets/ir-parts
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Merge in some parts of the jit IR stuff (not a lot)
2015-04-12 00:28:09 +02:00
Unknown W. Brackets
56f071d26a
x86jit: Support SIMD load/store with fastmem off.
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Which is a lot faster, since it usually takes the fast path.
2015-04-11 01:22:50 -07:00
Henrik Rydgård
81dec36da8
Use an accessor to read the compilerPC.
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In the IR it will be read from the block.
2015-04-11 01:14:37 -07:00
Henrik Rydgård